1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include "acpi.h"
6 #include "chan.h"
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "phy.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15 #include "txrx.h"
16 #include "util.h"
17
rtw89_phy0_phy1_offset(struct rtw89_dev * rtwdev,u32 addr)18 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr)
19 {
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
21
22 return phy->phy0_phy1_offset(rtwdev, addr);
23 }
24
get_max_amsdu_len(struct rtw89_dev * rtwdev,const struct rtw89_ra_report * report)25 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev,
26 const struct rtw89_ra_report *report)
27 {
28 u32 bit_rate = report->bit_rate;
29
30 /* lower than ofdm, do not aggregate */
31 if (bit_rate < 550)
32 return 1;
33
34 /* avoid AMSDU for legacy rate */
35 if (report->might_fallback_legacy)
36 return 1;
37
38 /* lower than 20M vht 2ss mcs8, make it small */
39 if (bit_rate < 1800)
40 return 1200;
41
42 /* lower than 40M vht 2ss mcs9, make it medium */
43 if (bit_rate < 4000)
44 return 2600;
45
46 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */
47 if (bit_rate < 7000)
48 return 3500;
49
50 return rtwdev->chip->max_amsdu_limit;
51 }
52
get_mcs_ra_mask(u16 mcs_map,u8 highest_mcs,u8 gap)53 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap)
54 {
55 u64 ra_mask = 0;
56 u8 mcs_cap;
57 int i, nss;
58
59 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) {
60 mcs_cap = mcs_map & 0x3;
61 switch (mcs_cap) {
62 case 2:
63 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss;
64 break;
65 case 1:
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss;
67 break;
68 case 0:
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss;
70 break;
71 default:
72 break;
73 }
74 }
75
76 return ra_mask;
77 }
78
get_he_ra_mask(struct ieee80211_link_sta * link_sta)79 static u64 get_he_ra_mask(struct ieee80211_link_sta *link_sta)
80 {
81 struct ieee80211_sta_he_cap cap = link_sta->he_cap;
82 u16 mcs_map;
83
84 switch (link_sta->bandwidth) {
85 case IEEE80211_STA_RX_BW_160:
86 if (cap.he_cap_elem.phy_cap_info[0] &
87 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G)
88 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80);
89 else
90 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160);
91 break;
92 default:
93 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80);
94 }
95
96 /* MCS11, MCS9, MCS7 */
97 return get_mcs_ra_mask(mcs_map, 11, 2);
98 }
99
get_eht_mcs_ra_mask(u8 * max_nss,u8 start_mcs,u8 n_nss)100 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss)
101 {
102 u64 nss_mcs_shift;
103 u64 nss_mcs_val;
104 u64 mask = 0;
105 int i, j;
106 u8 nss;
107
108 for (i = 0; i < n_nss; i++) {
109 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX);
110 if (!nss)
111 continue;
112
113 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0);
114
115 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16)
116 mask |= nss_mcs_val << nss_mcs_shift;
117 }
118
119 return mask;
120 }
121
get_eht_ra_mask(struct ieee80211_link_sta * link_sta)122 static u64 get_eht_ra_mask(struct ieee80211_link_sta *link_sta)
123 {
124 struct ieee80211_sta_eht_cap *eht_cap = &link_sta->eht_cap;
125 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz;
126 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss;
127 u8 *he_phy_cap = link_sta->he_cap.he_cap_elem.phy_cap_info;
128
129 switch (link_sta->bandwidth) {
130 case IEEE80211_STA_RX_BW_320:
131 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320;
132 /* MCS 9, 11, 13 */
133 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
134 case IEEE80211_STA_RX_BW_160:
135 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160;
136 /* MCS 9, 11, 13 */
137 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
138 case IEEE80211_STA_RX_BW_20:
139 if (!(he_phy_cap[0] &
140 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) {
141 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz;
142 /* MCS 7, 9, 11, 13 */
143 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4);
144 }
145 fallthrough;
146 case IEEE80211_STA_RX_BW_80:
147 default:
148 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80;
149 /* MCS 9, 11, 13 */
150 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3);
151 }
152 }
153
154 #define RA_FLOOR_TABLE_SIZE 7
155 #define RA_FLOOR_UP_GAP 3
rtw89_phy_ra_mask_rssi(struct rtw89_dev * rtwdev,u8 rssi,u8 ratr_state)156 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi,
157 u8 ratr_state)
158 {
159 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100};
160 u8 rssi_lv = 0;
161 u8 i;
162
163 rssi >>= 1;
164 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
165 if (i >= ratr_state)
166 rssi_lv_t[i] += RA_FLOOR_UP_GAP;
167 if (rssi < rssi_lv_t[i]) {
168 rssi_lv = i;
169 break;
170 }
171 }
172 if (rssi_lv == 0)
173 return 0xffffffffffffffffULL;
174 else if (rssi_lv == 1)
175 return 0xfffffffffffffff0ULL;
176 else if (rssi_lv == 2)
177 return 0xffffffffffffefe0ULL;
178 else if (rssi_lv == 3)
179 return 0xffffffffffffcfc0ULL;
180 else if (rssi_lv == 4)
181 return 0xffffffffffff8f80ULL;
182 else if (rssi_lv >= 5)
183 return 0xffffffffffff0f00ULL;
184
185 return 0xffffffffffffffffULL;
186 }
187
rtw89_phy_ra_mask_recover(u64 ra_mask,u64 ra_mask_bak)188 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak)
189 {
190 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0)
191 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
192
193 if (ra_mask == 0)
194 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES));
195
196 return ra_mask;
197 }
198
rtw89_phy_ra_mask_cfg(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan)199 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev,
200 struct rtw89_sta_link *rtwsta_link,
201 struct ieee80211_link_sta *link_sta,
202 const struct rtw89_chan *chan)
203 {
204 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
205 enum nl80211_band band;
206 u64 cfg_mask;
207
208 if (!rtwsta_link->use_cfg_mask)
209 return -1;
210
211 switch (chan->band_type) {
212 case RTW89_BAND_2G:
213 band = NL80211_BAND_2GHZ;
214 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy,
215 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES);
216 break;
217 case RTW89_BAND_5G:
218 band = NL80211_BAND_5GHZ;
219 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy,
220 RA_MASK_OFDM_RATES);
221 break;
222 case RTW89_BAND_6G:
223 band = NL80211_BAND_6GHZ;
224 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy,
225 RA_MASK_OFDM_RATES);
226 break;
227 default:
228 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type);
229 return -1;
230 }
231
232 if (link_sta->he_cap.has_he) {
233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0],
234 RA_MASK_HE_1SS_RATES);
235 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1],
236 RA_MASK_HE_2SS_RATES);
237 } else if (link_sta->vht_cap.vht_supported) {
238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0],
239 RA_MASK_VHT_1SS_RATES);
240 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1],
241 RA_MASK_VHT_2SS_RATES);
242 } else if (link_sta->ht_cap.ht_supported) {
243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0],
244 RA_MASK_HT_1SS_RATES);
245 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1],
246 RA_MASK_HT_2SS_RATES);
247 }
248
249 return cfg_mask;
250 }
251
252 static const u64
253 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES,
254 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES};
255 static const u64
256 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES,
257 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES};
258 static const u64
259 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES,
260 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES};
261 static const u64
262 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES,
263 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES};
264 static const u64
265 rtw89_ra_mask_eht_mcs0_11[4] = {RA_MASK_EHT_1SS_MCS0_11, RA_MASK_EHT_2SS_MCS0_11,
266 RA_MASK_EHT_3SS_MCS0_11, RA_MASK_EHT_4SS_MCS0_11};
267
rtw89_phy_ra_gi_ltf(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,const struct rtw89_chan * chan,bool * fix_giltf_en,u8 * fix_giltf)268 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev,
269 struct rtw89_sta_link *rtwsta_link,
270 struct ieee80211_link_sta *link_sta,
271 const struct rtw89_chan *chan,
272 bool *fix_giltf_en, u8 *fix_giltf)
273 {
274 struct cfg80211_bitrate_mask *mask = &rtwsta_link->mask;
275 u8 band = chan->band_type;
276 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
277 u8 he_ltf = mask->control[nl_band].he_ltf;
278 u8 he_gi = mask->control[nl_band].he_gi;
279
280 *fix_giltf_en = true;
281
282 if (rtwdev->chip->chip_id == RTL8852C &&
283 chan->band_width == RTW89_CHANNEL_WIDTH_160 &&
284 rtw89_sta_link_has_su_mu_4xhe08(link_sta))
285 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
286 else
287 *fix_giltf = RTW89_GILTF_2XHE08;
288
289 if (!(rtwsta_link->use_cfg_mask && link_sta->he_cap.has_he))
290 return;
291
292 if (he_ltf == 2 && he_gi == 2) {
293 *fix_giltf = RTW89_GILTF_LGI_4XHE32;
294 } else if (he_ltf == 2 && he_gi == 0) {
295 *fix_giltf = RTW89_GILTF_SGI_4XHE08;
296 } else if (he_ltf == 1 && he_gi == 1) {
297 *fix_giltf = RTW89_GILTF_2XHE16;
298 } else if (he_ltf == 1 && he_gi == 0) {
299 *fix_giltf = RTW89_GILTF_2XHE08;
300 } else if (he_ltf == 0 && he_gi == 1) {
301 *fix_giltf = RTW89_GILTF_1XHE16;
302 } else if (he_ltf == 0 && he_gi == 0) {
303 *fix_giltf = RTW89_GILTF_1XHE08;
304 }
305 }
306
rtw89_phy_ra_sta_update(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,bool p2p,bool csi)307 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev,
308 struct rtw89_vif_link *rtwvif_link,
309 struct rtw89_sta_link *rtwsta_link,
310 struct ieee80211_link_sta *link_sta,
311 bool p2p, bool csi)
312 {
313 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
314 struct rtw89_ra_info *ra = &rtwsta_link->ra;
315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
316 rtwvif_link->chanctx_idx);
317 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates;
318 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi);
319 u64 ra_mask = 0;
320 u64 ra_mask_bak;
321 u8 mode = 0;
322 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY;
323 u8 bw_mode = 0;
324 u8 stbc_en = 0;
325 u8 ldpc_en = 0;
326 u8 fix_giltf = 0;
327 u8 i;
328 bool sgi = false;
329 bool fix_giltf_en = false;
330
331 memset(ra, 0, sizeof(*ra));
332 /* Set the ra mask from sta's capability */
333 if (link_sta->eht_cap.has_eht) {
334 mode |= RTW89_RA_MODE_EHT;
335 ra_mask |= get_eht_ra_mask(link_sta);
336
337 if (rtwdev->hal.no_mcs_12_13)
338 high_rate_masks = rtw89_ra_mask_eht_mcs0_11;
339 else
340 high_rate_masks = rtw89_ra_mask_eht_rates;
341
342 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
343 chan, &fix_giltf_en, &fix_giltf);
344 } else if (link_sta->he_cap.has_he) {
345 mode |= RTW89_RA_MODE_HE;
346 csi_mode = RTW89_RA_RPT_MODE_HE;
347 ra_mask |= get_he_ra_mask(link_sta);
348 high_rate_masks = rtw89_ra_mask_he_rates;
349 if (link_sta->he_cap.he_cap_elem.phy_cap_info[2] &
350 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ)
351 stbc_en = 1;
352 if (link_sta->he_cap.he_cap_elem.phy_cap_info[1] &
353 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD)
354 ldpc_en = 1;
355 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta_link, link_sta,
356 chan, &fix_giltf_en, &fix_giltf);
357 } else if (link_sta->vht_cap.vht_supported) {
358 u16 mcs_map = le16_to_cpu(link_sta->vht_cap.vht_mcs.rx_mcs_map);
359
360 mode |= RTW89_RA_MODE_VHT;
361 csi_mode = RTW89_RA_RPT_MODE_VHT;
362 /* MCS9 (non-20MHz), MCS8, MCS7 */
363 if (link_sta->bandwidth == IEEE80211_STA_RX_BW_20)
364 ra_mask |= get_mcs_ra_mask(mcs_map, 8, 1);
365 else
366 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1);
367 high_rate_masks = rtw89_ra_mask_vht_rates;
368 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK)
369 stbc_en = 1;
370 if (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC)
371 ldpc_en = 1;
372 } else if (link_sta->ht_cap.ht_supported) {
373 mode |= RTW89_RA_MODE_HT;
374 csi_mode = RTW89_RA_RPT_MODE_HT;
375 ra_mask |= ((u64)link_sta->ht_cap.mcs.rx_mask[3] << 48) |
376 ((u64)link_sta->ht_cap.mcs.rx_mask[2] << 36) |
377 ((u64)link_sta->ht_cap.mcs.rx_mask[1] << 24) |
378 ((u64)link_sta->ht_cap.mcs.rx_mask[0] << 12);
379 high_rate_masks = rtw89_ra_mask_ht_rates;
380 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_RX_STBC)
381 stbc_en = 1;
382 if (link_sta->ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING)
383 ldpc_en = 1;
384 }
385
386 switch (chan->band_type) {
387 case RTW89_BAND_2G:
388 ra_mask |= link_sta->supp_rates[NL80211_BAND_2GHZ];
389 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xf)
390 mode |= RTW89_RA_MODE_CCK;
391 if (link_sta->supp_rates[NL80211_BAND_2GHZ] & 0xff0)
392 mode |= RTW89_RA_MODE_OFDM;
393 break;
394 case RTW89_BAND_5G:
395 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_5GHZ] << 4;
396 mode |= RTW89_RA_MODE_OFDM;
397 break;
398 case RTW89_BAND_6G:
399 ra_mask |= (u64)link_sta->supp_rates[NL80211_BAND_6GHZ] << 4;
400 mode |= RTW89_RA_MODE_OFDM;
401 break;
402 default:
403 rtw89_err(rtwdev, "Unknown band type\n");
404 break;
405 }
406
407 ra_mask_bak = ra_mask;
408
409 if (mode >= RTW89_RA_MODE_HT) {
410 u64 mask = 0;
411 for (i = 0; i < rtwdev->hal.tx_nss; i++)
412 mask |= high_rate_masks[i];
413 if (mode & RTW89_RA_MODE_OFDM)
414 mask |= RA_MASK_SUBOFDM_RATES;
415 if (mode & RTW89_RA_MODE_CCK)
416 mask |= RA_MASK_SUBCCK_RATES;
417 ra_mask &= mask;
418 } else if (mode & RTW89_RA_MODE_OFDM) {
419 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES);
420 }
421
422 if (mode != RTW89_RA_MODE_CCK)
423 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0);
424
425 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak);
426 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
427
428 switch (link_sta->bandwidth) {
429 case IEEE80211_STA_RX_BW_160:
430 bw_mode = RTW89_CHANNEL_WIDTH_160;
431 sgi = link_sta->vht_cap.vht_supported &&
432 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160);
433 break;
434 case IEEE80211_STA_RX_BW_80:
435 bw_mode = RTW89_CHANNEL_WIDTH_80;
436 sgi = link_sta->vht_cap.vht_supported &&
437 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80);
438 break;
439 case IEEE80211_STA_RX_BW_40:
440 bw_mode = RTW89_CHANNEL_WIDTH_40;
441 sgi = link_sta->ht_cap.ht_supported &&
442 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40);
443 break;
444 default:
445 bw_mode = RTW89_CHANNEL_WIDTH_20;
446 sgi = link_sta->ht_cap.ht_supported &&
447 (link_sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20);
448 break;
449 }
450
451 if (link_sta->he_cap.he_cap_elem.phy_cap_info[3] &
452 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM)
453 ra->dcm_cap = 1;
454
455 if (rate_pattern->enable && !p2p) {
456 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta_link, link_sta, chan);
457 ra_mask &= rate_pattern->ra_mask;
458 mode = rate_pattern->ra_mode;
459 }
460
461 ra->bw_cap = bw_mode;
462 ra->er_cap = rtwsta_link->er_cap;
463 ra->mode_ctrl = mode;
464 ra->macid = rtwsta_link->mac_id;
465 ra->stbc_cap = stbc_en;
466 ra->ldpc_cap = ldpc_en;
467 ra->ss_num = min(link_sta->rx_nss, rtwdev->hal.tx_nss) - 1;
468 ra->en_sgi = sgi;
469 ra->ra_mask = ra_mask;
470 ra->fix_giltf_en = fix_giltf_en;
471 ra->fix_giltf = fix_giltf;
472
473 if (!csi)
474 return;
475
476 ra->fixed_csi_rate_en = false;
477 ra->ra_csi_rate_en = true;
478 ra->cr_tbl_sel = false;
479 ra->band_num = rtwvif_link->phy_idx;
480 ra->csi_bw = bw_mode;
481 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32;
482 ra->csi_mcs_ss_idx = 5;
483 ra->csi_mode = csi_mode;
484 }
485
rtw89_phy_ra_update_sta_link(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u32 changed)486 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
487 struct rtw89_sta_link *rtwsta_link,
488 u32 changed)
489 {
490 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
491 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
492 struct rtw89_ra_info *ra = &rtwsta_link->ra;
493 struct ieee80211_link_sta *link_sta;
494
495 rcu_read_lock();
496
497 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
498 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
499 link_sta, vif->p2p, false);
500
501 rcu_read_unlock();
502
503 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED)
504 ra->upd_mask = 1;
505 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED))
506 ra->upd_bw_nss_mask = 1;
507
508 rtw89_debug(rtwdev, RTW89_DBG_RA,
509 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d",
510 ra->macid,
511 ra->bw_cap,
512 ra->ss_num,
513 ra->en_sgi,
514 ra->giltf);
515
516 rtw89_fw_h2c_ra(rtwdev, ra, false);
517 }
518
rtw89_phy_ra_update_sta(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,u32 changed)519 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
520 u32 changed)
521 {
522 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
523 struct rtw89_sta_link *rtwsta_link;
524 unsigned int link_id;
525
526 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
527 rtw89_phy_ra_update_sta_link(rtwdev, rtwsta_link, changed);
528 }
529
__check_rate_pattern(struct rtw89_phy_rate_pattern * next,u16 rate_base,u64 ra_mask,u8 ra_mode,u32 rate_ctrl,u32 ctrl_skip,bool force)530 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next,
531 u16 rate_base, u64 ra_mask, u8 ra_mode,
532 u32 rate_ctrl, u32 ctrl_skip, bool force)
533 {
534 u8 n, c;
535
536 if (rate_ctrl == ctrl_skip)
537 return true;
538
539 n = hweight32(rate_ctrl);
540 if (n == 0)
541 return true;
542
543 if (force && n != 1)
544 return false;
545
546 if (next->enable)
547 return false;
548
549 c = __fls(rate_ctrl);
550 next->rate = rate_base + c;
551 next->ra_mode = ra_mode;
552 next->ra_mask = ra_mask;
553 next->enable = true;
554
555 return true;
556 }
557
558 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \
559 { \
560 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \
561 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \
562 }
563
564 static
__rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const struct cfg80211_bitrate_mask * mask)565 void __rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
566 struct rtw89_vif_link *rtwvif_link,
567 const struct cfg80211_bitrate_mask *mask)
568 {
569 struct ieee80211_supported_band *sband;
570 struct rtw89_phy_rate_pattern next_pattern = {0};
571 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
572 rtwvif_link->chanctx_idx);
573 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = {
574 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0),
575 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0),
576 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0),
577 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0),
578 };
579 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = {
580 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0),
581 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0),
582 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0),
583 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0),
584 };
585 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = {
586 RTW89_HW_RATE_BY_CHIP_GEN(MCS0),
587 RTW89_HW_RATE_BY_CHIP_GEN(MCS8),
588 RTW89_HW_RATE_BY_CHIP_GEN(MCS16),
589 RTW89_HW_RATE_BY_CHIP_GEN(MCS24),
590 };
591 u8 band = chan->band_type;
592 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
593 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
594 u8 tx_nss = rtwdev->hal.tx_nss;
595 u8 i;
596
597 for (i = 0; i < tx_nss; i++)
598 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen],
599 RA_MASK_HE_RATES, RTW89_RA_MODE_HE,
600 mask->control[nl_band].he_mcs[i],
601 0, true))
602 goto out;
603
604 for (i = 0; i < tx_nss; i++)
605 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen],
606 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT,
607 mask->control[nl_band].vht_mcs[i],
608 0, true))
609 goto out;
610
611 for (i = 0; i < tx_nss; i++)
612 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen],
613 RA_MASK_HT_RATES, RTW89_RA_MODE_HT,
614 mask->control[nl_band].ht_mcs[i],
615 0, true))
616 goto out;
617
618 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and
619 * require at least one basic rate for ieee80211_set_bitrate_mask,
620 * so the decision just depends on if all bitrates are set or not.
621 */
622 sband = rtwdev->hw->wiphy->bands[nl_band];
623 if (band == RTW89_BAND_2G) {
624 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1,
625 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES,
626 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM,
627 mask->control[nl_band].legacy,
628 BIT(sband->n_bitrates) - 1, false))
629 goto out;
630 } else {
631 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6,
632 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM,
633 mask->control[nl_band].legacy,
634 BIT(sband->n_bitrates) - 1, false))
635 goto out;
636 }
637
638 if (!next_pattern.enable)
639 goto out;
640
641 rtwvif_link->rate_pattern = next_pattern;
642 rtw89_debug(rtwdev, RTW89_DBG_RA,
643 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n",
644 next_pattern.rate,
645 next_pattern.ra_mask,
646 next_pattern.ra_mode);
647 return;
648
649 out:
650 rtwvif_link->rate_pattern.enable = false;
651 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n");
652 }
653
rtw89_phy_rate_pattern_vif(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,const struct cfg80211_bitrate_mask * mask)654 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
655 struct ieee80211_vif *vif,
656 const struct cfg80211_bitrate_mask *mask)
657 {
658 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
659 struct rtw89_vif_link *rtwvif_link;
660 unsigned int link_id;
661
662 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
663 __rtw89_phy_rate_pattern_vif(rtwdev, rtwvif_link, mask);
664 }
665
rtw89_phy_ra_update_sta_iter(void * data,struct ieee80211_sta * sta)666 static void rtw89_phy_ra_update_sta_iter(void *data, struct ieee80211_sta *sta)
667 {
668 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data;
669
670 rtw89_phy_ra_update_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED);
671 }
672
rtw89_phy_ra_update(struct rtw89_dev * rtwdev)673 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev)
674 {
675 ieee80211_iterate_stations_atomic(rtwdev->hw,
676 rtw89_phy_ra_update_sta_iter,
677 rtwdev);
678 }
679
rtw89_phy_ra_assoc(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)680 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link)
681 {
682 struct rtw89_vif_link *rtwvif_link = rtwsta_link->rtwvif_link;
683 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
684 struct rtw89_ra_info *ra = &rtwsta_link->ra;
685 u8 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR;
686 struct ieee80211_link_sta *link_sta;
687 bool csi;
688
689 rcu_read_lock();
690
691 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
692 csi = rtw89_sta_has_beamformer_cap(link_sta);
693
694 rtw89_phy_ra_sta_update(rtwdev, rtwvif_link, rtwsta_link,
695 link_sta, vif->p2p, csi);
696
697 rcu_read_unlock();
698
699 if (rssi > 40)
700 ra->init_rate_lv = 1;
701 else if (rssi > 20)
702 ra->init_rate_lv = 2;
703 else if (rssi > 1)
704 ra->init_rate_lv = 3;
705 else
706 ra->init_rate_lv = 0;
707 ra->upd_all = 1;
708 rtw89_debug(rtwdev, RTW89_DBG_RA,
709 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d",
710 ra->macid,
711 ra->mode_ctrl,
712 ra->bw_cap,
713 ra->ss_num,
714 ra->init_rate_lv);
715 rtw89_debug(rtwdev, RTW89_DBG_RA,
716 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d",
717 ra->dcm_cap,
718 ra->er_cap,
719 ra->ldpc_cap,
720 ra->stbc_cap,
721 ra->en_sgi,
722 ra->giltf);
723
724 rtw89_fw_h2c_ra(rtwdev, ra, csi);
725 }
726
rtw89_phy_get_txsc(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)727 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
728 const struct rtw89_chan *chan,
729 enum rtw89_bandwidth dbw)
730 {
731 enum rtw89_bandwidth cbw = chan->band_width;
732 u8 pri_ch = chan->primary_channel;
733 u8 central_ch = chan->channel;
734 u8 txsc_idx = 0;
735 u8 tmp = 0;
736
737 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
738 return txsc_idx;
739
740 switch (cbw) {
741 case RTW89_CHANNEL_WIDTH_40:
742 txsc_idx = pri_ch > central_ch ? 1 : 2;
743 break;
744 case RTW89_CHANNEL_WIDTH_80:
745 if (dbw == RTW89_CHANNEL_WIDTH_20) {
746 if (pri_ch > central_ch)
747 txsc_idx = (pri_ch - central_ch) >> 1;
748 else
749 txsc_idx = ((central_ch - pri_ch) >> 1) + 1;
750 } else {
751 txsc_idx = pri_ch > central_ch ? 9 : 10;
752 }
753 break;
754 case RTW89_CHANNEL_WIDTH_160:
755 if (pri_ch > central_ch)
756 tmp = (pri_ch - central_ch) >> 1;
757 else
758 tmp = ((central_ch - pri_ch) >> 1) + 1;
759
760 if (dbw == RTW89_CHANNEL_WIDTH_20) {
761 txsc_idx = tmp;
762 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
763 if (tmp == 1 || tmp == 3)
764 txsc_idx = 9;
765 else if (tmp == 5 || tmp == 7)
766 txsc_idx = 11;
767 else if (tmp == 2 || tmp == 4)
768 txsc_idx = 10;
769 else if (tmp == 6 || tmp == 8)
770 txsc_idx = 12;
771 else
772 return 0xff;
773 } else {
774 txsc_idx = pri_ch > central_ch ? 13 : 14;
775 }
776 break;
777 case RTW89_CHANNEL_WIDTH_80_80:
778 if (dbw == RTW89_CHANNEL_WIDTH_20) {
779 if (pri_ch > central_ch)
780 txsc_idx = (10 - (pri_ch - central_ch)) >> 1;
781 else
782 txsc_idx = ((central_ch - pri_ch) >> 1) + 5;
783 } else if (dbw == RTW89_CHANNEL_WIDTH_40) {
784 txsc_idx = pri_ch > central_ch ? 10 : 12;
785 } else {
786 txsc_idx = 14;
787 }
788 break;
789 default:
790 break;
791 }
792
793 return txsc_idx;
794 }
795 EXPORT_SYMBOL(rtw89_phy_get_txsc);
796
rtw89_phy_get_txsb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_bandwidth dbw)797 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
798 enum rtw89_bandwidth dbw)
799 {
800 enum rtw89_bandwidth cbw = chan->band_width;
801 u8 pri_ch = chan->primary_channel;
802 u8 central_ch = chan->channel;
803 u8 txsb_idx = 0;
804
805 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20)
806 return txsb_idx;
807
808 switch (cbw) {
809 case RTW89_CHANNEL_WIDTH_40:
810 txsb_idx = pri_ch > central_ch ? 1 : 0;
811 break;
812 case RTW89_CHANNEL_WIDTH_80:
813 if (dbw == RTW89_CHANNEL_WIDTH_20)
814 txsb_idx = (pri_ch - central_ch + 6) / 4;
815 else
816 txsb_idx = pri_ch > central_ch ? 1 : 0;
817 break;
818 case RTW89_CHANNEL_WIDTH_160:
819 if (dbw == RTW89_CHANNEL_WIDTH_20)
820 txsb_idx = (pri_ch - central_ch + 14) / 4;
821 else if (dbw == RTW89_CHANNEL_WIDTH_40)
822 txsb_idx = (pri_ch - central_ch + 12) / 8;
823 else
824 txsb_idx = pri_ch > central_ch ? 1 : 0;
825 break;
826 case RTW89_CHANNEL_WIDTH_320:
827 if (dbw == RTW89_CHANNEL_WIDTH_20)
828 txsb_idx = (pri_ch - central_ch + 30) / 4;
829 else if (dbw == RTW89_CHANNEL_WIDTH_40)
830 txsb_idx = (pri_ch - central_ch + 28) / 8;
831 else if (dbw == RTW89_CHANNEL_WIDTH_80)
832 txsb_idx = (pri_ch - central_ch + 24) / 16;
833 else
834 txsb_idx = pri_ch > central_ch ? 1 : 0;
835 break;
836 default:
837 break;
838 }
839
840 return txsb_idx;
841 }
842 EXPORT_SYMBOL(rtw89_phy_get_txsb);
843
rtw89_phy_check_swsi_busy(struct rtw89_dev * rtwdev)844 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev)
845 {
846 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) ||
847 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1);
848 }
849
rtw89_phy_read_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)850 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
851 u32 addr, u32 mask)
852 {
853 const struct rtw89_chip_info *chip = rtwdev->chip;
854 const u32 *base_addr = chip->rf_base_addr;
855 u32 val, direct_addr;
856
857 if (rf_path >= rtwdev->chip->rf_path_num) {
858 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
859 return INV_RF_DATA;
860 }
861
862 addr &= 0xff;
863 direct_addr = base_addr[rf_path] + (addr << 2);
864 mask &= RFREG_MASK;
865
866 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask);
867
868 return val;
869 }
870 EXPORT_SYMBOL(rtw89_phy_read_rf);
871
rtw89_phy_read_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)872 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev,
873 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
874 {
875 bool busy;
876 bool done;
877 u32 val;
878 int ret;
879
880 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
881 1, 30, false, rtwdev);
882 if (ret) {
883 rtw89_err(rtwdev, "read rf busy swsi\n");
884 return INV_RF_DATA;
885 }
886
887 mask &= RFREG_MASK;
888
889 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) |
890 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr);
891 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val);
892 udelay(2);
893
894 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1,
895 30, false, rtwdev, R_SWSI_V1,
896 B_SWSI_R_DATA_DONE_V1);
897 if (ret) {
898 rtw89_err(rtwdev, "read swsi busy\n");
899 return INV_RF_DATA;
900 }
901
902 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask);
903 }
904
rtw89_phy_read_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)905 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
906 u32 addr, u32 mask)
907 {
908 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
909
910 if (rf_path >= rtwdev->chip->rf_path_num) {
911 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
912 return INV_RF_DATA;
913 }
914
915 if (ad_sel)
916 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
917 else
918 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask);
919 }
920 EXPORT_SYMBOL(rtw89_phy_read_rf_v1);
921
rtw89_phy_read_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr)922 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev,
923 enum rtw89_rf_path rf_path, u32 addr)
924 {
925 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24};
926 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC};
927 bool busy, done;
928 int ret;
929 u32 val;
930
931 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1);
932 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
933 1, 3800, false,
934 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY);
935 if (ret) {
936 rtw89_warn(rtwdev, "poll HWSI is busy\n");
937 return INV_RF_DATA;
938 }
939
940 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr);
941 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1);
942 udelay(2);
943
944 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done,
945 1, 3800, false,
946 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE);
947 if (ret) {
948 rtw89_warn(rtwdev, "read HWSI is busy\n");
949 val = INV_RF_DATA;
950 goto out;
951 }
952
953 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK);
954 out:
955 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0);
956
957 return val;
958 }
959
rtw89_phy_read_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)960 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev,
961 enum rtw89_rf_path rf_path, u32 addr, u32 mask)
962 {
963 u32 val;
964
965 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
966
967 return (val & mask) >> __ffs(mask);
968 }
969
rtw89_phy_read_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask)970 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
971 u32 addr, u32 mask)
972 {
973 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
974
975 if (rf_path >= rtwdev->chip->rf_path_num) {
976 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
977 return INV_RF_DATA;
978 }
979
980 if (ad_sel)
981 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask);
982 else
983 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask);
984 }
985 EXPORT_SYMBOL(rtw89_phy_read_rf_v2);
986
rtw89_phy_write_rf(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)987 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
988 u32 addr, u32 mask, u32 data)
989 {
990 const struct rtw89_chip_info *chip = rtwdev->chip;
991 const u32 *base_addr = chip->rf_base_addr;
992 u32 direct_addr;
993
994 if (rf_path >= rtwdev->chip->rf_path_num) {
995 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
996 return false;
997 }
998
999 addr &= 0xff;
1000 direct_addr = base_addr[rf_path] + (addr << 2);
1001 mask &= RFREG_MASK;
1002
1003 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data);
1004
1005 /* delay to ensure writing properly */
1006 udelay(1);
1007
1008 return true;
1009 }
1010 EXPORT_SYMBOL(rtw89_phy_write_rf);
1011
rtw89_phy_write_rf_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1012 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev,
1013 enum rtw89_rf_path rf_path, u32 addr, u32 mask,
1014 u32 data)
1015 {
1016 u8 bit_shift;
1017 u32 val;
1018 bool busy, b_msk_en = false;
1019 int ret;
1020
1021 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy,
1022 1, 30, false, rtwdev);
1023 if (ret) {
1024 rtw89_err(rtwdev, "write rf busy swsi\n");
1025 return false;
1026 }
1027
1028 data &= RFREG_MASK;
1029 mask &= RFREG_MASK;
1030
1031 if (mask != RFREG_MASK) {
1032 b_msk_en = true;
1033 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK,
1034 mask);
1035 bit_shift = __ffs(mask);
1036 data = (data << bit_shift) & RFREG_MASK;
1037 }
1038
1039 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) |
1040 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) |
1041 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) |
1042 FIELD_PREP(B_SWSI_DATA_VAL_V1, data);
1043
1044 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val);
1045
1046 return true;
1047 }
1048
rtw89_phy_write_rf_v1(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1049 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1050 u32 addr, u32 mask, u32 data)
1051 {
1052 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr);
1053
1054 if (rf_path >= rtwdev->chip->rf_path_num) {
1055 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1056 return false;
1057 }
1058
1059 if (ad_sel)
1060 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1061 else
1062 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data);
1063 }
1064 EXPORT_SYMBOL(rtw89_phy_write_rf_v1);
1065
1066 static
rtw89_phy_write_full_rf_v2_a(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 data)1067 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1068 u32 addr, u32 data)
1069 {
1070 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24};
1071 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0};
1072 bool busy;
1073 u32 val;
1074 int ret;
1075
1076 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy,
1077 1, 3800, false,
1078 rtwdev, addr_is_idle[rf_path], BIT(29));
1079 if (ret) {
1080 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__);
1081 return false;
1082 }
1083
1084 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) |
1085 u32_encode_bits(data, B_HWSI_DATA_VAL);
1086
1087 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val);
1088
1089 return true;
1090 }
1091
1092 static
rtw89_phy_write_rf_a_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1093 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1094 u32 addr, u32 mask, u32 data)
1095 {
1096 u32 val;
1097
1098 if (mask == RFREG_MASK) {
1099 val = data;
1100 } else {
1101 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr);
1102 val &= ~mask;
1103 val |= (data << __ffs(mask)) & mask;
1104 }
1105
1106 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val);
1107 }
1108
rtw89_phy_write_rf_v2(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path,u32 addr,u32 mask,u32 data)1109 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1110 u32 addr, u32 mask, u32 data)
1111 {
1112 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK);
1113
1114 if (rf_path >= rtwdev->chip->rf_path_num) {
1115 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path);
1116 return INV_RF_DATA;
1117 }
1118
1119 if (ad_sel)
1120 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data);
1121 else
1122 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data);
1123 }
1124 EXPORT_SYMBOL(rtw89_phy_write_rf_v2);
1125
rtw89_chip_rf_v1(struct rtw89_dev * rtwdev)1126 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev)
1127 {
1128 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1;
1129 }
1130
__rtw89_phy_bb_reset(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)1131 static void __rtw89_phy_bb_reset(struct rtw89_dev *rtwdev,
1132 enum rtw89_phy_idx phy_idx)
1133 {
1134 const struct rtw89_chip_info *chip = rtwdev->chip;
1135
1136 chip->ops->bb_reset(rtwdev, phy_idx);
1137 }
1138
rtw89_phy_bb_reset(struct rtw89_dev * rtwdev)1139 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev)
1140 {
1141 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0);
1142 if (rtwdev->dbcc_en)
1143 __rtw89_phy_bb_reset(rtwdev, RTW89_PHY_1);
1144 }
1145
rtw89_phy_config_bb_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1146 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev,
1147 const struct rtw89_reg2_def *reg,
1148 enum rtw89_rf_path rf_path,
1149 void *extra_data)
1150 {
1151 u32 addr;
1152
1153 if (reg->addr == 0xfe) {
1154 mdelay(50);
1155 } else if (reg->addr == 0xfd) {
1156 mdelay(5);
1157 } else if (reg->addr == 0xfc) {
1158 mdelay(1);
1159 } else if (reg->addr == 0xfb) {
1160 udelay(50);
1161 } else if (reg->addr == 0xfa) {
1162 udelay(5);
1163 } else if (reg->addr == 0xf9) {
1164 udelay(1);
1165 } else if (reg->data == BYPASS_CR_DATA) {
1166 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr);
1167 } else {
1168 addr = reg->addr;
1169
1170 if ((uintptr_t)extra_data == RTW89_PHY_1)
1171 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr);
1172
1173 rtw89_phy_write32(rtwdev, addr, reg->data);
1174 }
1175 }
1176
1177 union rtw89_phy_bb_gain_arg {
1178 u32 addr;
1179 struct {
1180 union {
1181 u8 type;
1182 struct {
1183 u8 rxsc_start:4;
1184 u8 bw:4;
1185 };
1186 };
1187 u8 path;
1188 u8 gain_band;
1189 u8 cfg_type;
1190 };
1191 } __packed;
1192
1193 static void
rtw89_phy_cfg_bb_gain_error(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1194 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev,
1195 union rtw89_phy_bb_gain_arg arg, u32 data)
1196 {
1197 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1198 u8 type = arg.type;
1199 u8 path = arg.path;
1200 u8 gband = arg.gain_band;
1201 int i;
1202
1203 switch (type) {
1204 case 0:
1205 for (i = 0; i < 4; i++, data >>= 8)
1206 gain->lna_gain[gband][path][i] = data & 0xff;
1207 break;
1208 case 1:
1209 for (i = 4; i < 7; i++, data >>= 8)
1210 gain->lna_gain[gband][path][i] = data & 0xff;
1211 break;
1212 case 2:
1213 for (i = 0; i < 2; i++, data >>= 8)
1214 gain->tia_gain[gband][path][i] = data & 0xff;
1215 break;
1216 default:
1217 rtw89_warn(rtwdev,
1218 "bb gain error {0x%x:0x%x} with unknown type: %d\n",
1219 arg.addr, data, type);
1220 break;
1221 }
1222 }
1223
1224 enum rtw89_phy_bb_rxsc_start_idx {
1225 RTW89_BB_RXSC_START_IDX_FULL = 0,
1226 RTW89_BB_RXSC_START_IDX_20 = 1,
1227 RTW89_BB_RXSC_START_IDX_20_1 = 5,
1228 RTW89_BB_RXSC_START_IDX_40 = 9,
1229 RTW89_BB_RXSC_START_IDX_80 = 13,
1230 };
1231
1232 static void
rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1233 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev,
1234 union rtw89_phy_bb_gain_arg arg, u32 data)
1235 {
1236 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1237 u8 rxsc_start = arg.rxsc_start;
1238 u8 bw = arg.bw;
1239 u8 path = arg.path;
1240 u8 gband = arg.gain_band;
1241 u8 rxsc;
1242 s8 ofst;
1243 int i;
1244
1245 switch (bw) {
1246 case RTW89_CHANNEL_WIDTH_20:
1247 gain->rpl_ofst_20[gband][path] = (s8)data;
1248 break;
1249 case RTW89_CHANNEL_WIDTH_40:
1250 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1251 gain->rpl_ofst_40[gband][path][0] = (s8)data;
1252 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1253 for (i = 0; i < 2; i++, data >>= 8) {
1254 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1255 ofst = (s8)(data & 0xff);
1256 gain->rpl_ofst_40[gband][path][rxsc] = ofst;
1257 }
1258 }
1259 break;
1260 case RTW89_CHANNEL_WIDTH_80:
1261 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1262 gain->rpl_ofst_80[gband][path][0] = (s8)data;
1263 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1264 for (i = 0; i < 4; i++, data >>= 8) {
1265 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1266 ofst = (s8)(data & 0xff);
1267 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1268 }
1269 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1270 for (i = 0; i < 2; i++, data >>= 8) {
1271 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1272 ofst = (s8)(data & 0xff);
1273 gain->rpl_ofst_80[gband][path][rxsc] = ofst;
1274 }
1275 }
1276 break;
1277 case RTW89_CHANNEL_WIDTH_160:
1278 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) {
1279 gain->rpl_ofst_160[gband][path][0] = (s8)data;
1280 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) {
1281 for (i = 0; i < 4; i++, data >>= 8) {
1282 rxsc = RTW89_BB_RXSC_START_IDX_20 + i;
1283 ofst = (s8)(data & 0xff);
1284 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1285 }
1286 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) {
1287 for (i = 0; i < 4; i++, data >>= 8) {
1288 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i;
1289 ofst = (s8)(data & 0xff);
1290 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1291 }
1292 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) {
1293 for (i = 0; i < 4; i++, data >>= 8) {
1294 rxsc = RTW89_BB_RXSC_START_IDX_40 + i;
1295 ofst = (s8)(data & 0xff);
1296 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1297 }
1298 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) {
1299 for (i = 0; i < 2; i++, data >>= 8) {
1300 rxsc = RTW89_BB_RXSC_START_IDX_80 + i;
1301 ofst = (s8)(data & 0xff);
1302 gain->rpl_ofst_160[gband][path][rxsc] = ofst;
1303 }
1304 }
1305 break;
1306 default:
1307 rtw89_warn(rtwdev,
1308 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n",
1309 arg.addr, data, bw);
1310 break;
1311 }
1312 }
1313
1314 static void
rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1315 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev,
1316 union rtw89_phy_bb_gain_arg arg, u32 data)
1317 {
1318 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1319 u8 type = arg.type;
1320 u8 path = arg.path;
1321 u8 gband = arg.gain_band;
1322 int i;
1323
1324 switch (type) {
1325 case 0:
1326 for (i = 0; i < 4; i++, data >>= 8)
1327 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1328 break;
1329 case 1:
1330 for (i = 4; i < 7; i++, data >>= 8)
1331 gain->lna_gain_bypass[gband][path][i] = data & 0xff;
1332 break;
1333 default:
1334 rtw89_warn(rtwdev,
1335 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n",
1336 arg.addr, data, type);
1337 break;
1338 }
1339 }
1340
1341 static void
rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev * rtwdev,union rtw89_phy_bb_gain_arg arg,u32 data)1342 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev,
1343 union rtw89_phy_bb_gain_arg arg, u32 data)
1344 {
1345 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax;
1346 u8 type = arg.type;
1347 u8 path = arg.path;
1348 u8 gband = arg.gain_band;
1349 int i;
1350
1351 switch (type) {
1352 case 0:
1353 for (i = 0; i < 4; i++, data >>= 8)
1354 gain->lna_op1db[gband][path][i] = data & 0xff;
1355 break;
1356 case 1:
1357 for (i = 4; i < 7; i++, data >>= 8)
1358 gain->lna_op1db[gband][path][i] = data & 0xff;
1359 break;
1360 case 2:
1361 for (i = 0; i < 4; i++, data >>= 8)
1362 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1363 break;
1364 case 3:
1365 for (i = 4; i < 8; i++, data >>= 8)
1366 gain->tia_lna_op1db[gband][path][i] = data & 0xff;
1367 break;
1368 default:
1369 rtw89_warn(rtwdev,
1370 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n",
1371 arg.addr, data, type);
1372 break;
1373 }
1374 }
1375
rtw89_phy_config_bb_gain_ax(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1376 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev,
1377 const struct rtw89_reg2_def *reg,
1378 enum rtw89_rf_path rf_path,
1379 void *extra_data)
1380 {
1381 const struct rtw89_chip_info *chip = rtwdev->chip;
1382 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr };
1383 struct rtw89_efuse *efuse = &rtwdev->efuse;
1384
1385 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR)
1386 return;
1387
1388 if (arg.path >= chip->rf_path_num)
1389 return;
1390
1391 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) {
1392 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n");
1393 return;
1394 }
1395
1396 switch (arg.cfg_type) {
1397 case 0:
1398 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data);
1399 break;
1400 case 1:
1401 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data);
1402 break;
1403 case 2:
1404 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data);
1405 break;
1406 case 3:
1407 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data);
1408 break;
1409 case 4:
1410 /* This cfg_type is only used by rfe_type >= 50 with eFEM */
1411 if (efuse->rfe_type < 50)
1412 break;
1413 fallthrough;
1414 default:
1415 rtw89_warn(rtwdev,
1416 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n",
1417 arg.addr, reg->data, arg.cfg_type);
1418 break;
1419 }
1420 }
1421
1422 static void
rtw89_phy_cofig_rf_reg_store(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,struct rtw89_fw_h2c_rf_reg_info * info)1423 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev,
1424 const struct rtw89_reg2_def *reg,
1425 enum rtw89_rf_path rf_path,
1426 struct rtw89_fw_h2c_rf_reg_info *info)
1427 {
1428 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE;
1429 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE;
1430
1431 if (page >= RTW89_H2C_RF_PAGE_NUM) {
1432 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d",
1433 rf_path, info->curr_idx);
1434 return;
1435 }
1436
1437 info->rtw89_phy_config_rf_h2c[page][idx] =
1438 cpu_to_le32((reg->addr << 20) | reg->data);
1439 info->curr_idx++;
1440 }
1441
rtw89_phy_config_rf_reg_fw(struct rtw89_dev * rtwdev,struct rtw89_fw_h2c_rf_reg_info * info)1442 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev,
1443 struct rtw89_fw_h2c_rf_reg_info *info)
1444 {
1445 u16 remain = info->curr_idx;
1446 u16 len = 0;
1447 u8 i;
1448 int ret = 0;
1449
1450 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) {
1451 rtw89_warn(rtwdev,
1452 "rf reg h2c total len %d larger than %d\n",
1453 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE);
1454 ret = -EINVAL;
1455 goto out;
1456 }
1457
1458 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) {
1459 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain;
1460 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i);
1461 if (ret)
1462 goto out;
1463 }
1464 out:
1465 info->curr_idx = 0;
1466
1467 return ret;
1468 }
1469
rtw89_phy_config_rf_reg_noio(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1470 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev,
1471 const struct rtw89_reg2_def *reg,
1472 enum rtw89_rf_path rf_path,
1473 void *extra_data)
1474 {
1475 u32 addr = reg->addr;
1476
1477 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb ||
1478 addr == 0xfa || addr == 0xf9)
1479 return;
1480
1481 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100)
1482 return;
1483
1484 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1485 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1486 }
1487
rtw89_phy_config_rf_reg(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1488 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
1489 const struct rtw89_reg2_def *reg,
1490 enum rtw89_rf_path rf_path,
1491 void *extra_data)
1492 {
1493 if (reg->addr == 0xfe) {
1494 mdelay(50);
1495 } else if (reg->addr == 0xfd) {
1496 mdelay(5);
1497 } else if (reg->addr == 0xfc) {
1498 mdelay(1);
1499 } else if (reg->addr == 0xfb) {
1500 udelay(50);
1501 } else if (reg->addr == 0xfa) {
1502 udelay(5);
1503 } else if (reg->addr == 0xf9) {
1504 udelay(1);
1505 } else {
1506 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data);
1507 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1508 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1509 }
1510 }
1511
rtw89_phy_config_rf_reg_v1(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * extra_data)1512 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
1513 const struct rtw89_reg2_def *reg,
1514 enum rtw89_rf_path rf_path,
1515 void *extra_data)
1516 {
1517 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data);
1518
1519 if (reg->addr < 0x100)
1520 return;
1521
1522 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path,
1523 (struct rtw89_fw_h2c_rf_reg_info *)extra_data);
1524 }
1525 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1);
1526
rtw89_phy_sel_headline(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,u32 * headline_size,u32 * headline_idx,u8 rfe,u8 cv)1527 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev,
1528 const struct rtw89_phy_table *table,
1529 u32 *headline_size, u32 *headline_idx,
1530 u8 rfe, u8 cv)
1531 {
1532 const struct rtw89_reg2_def *reg;
1533 u32 headline;
1534 u32 compare, target;
1535 u8 rfe_para, cv_para;
1536 u8 cv_max = 0;
1537 bool case_matched = false;
1538 u32 i;
1539
1540 for (i = 0; i < table->n_regs; i++) {
1541 reg = &table->regs[i];
1542 headline = get_phy_headline(reg->addr);
1543 if (headline != PHY_HEADLINE_VALID)
1544 break;
1545 }
1546 *headline_size = i;
1547 if (*headline_size == 0)
1548 return 0;
1549
1550 /* case 1: RFE match, CV match */
1551 compare = get_phy_compare(rfe, cv);
1552 for (i = 0; i < *headline_size; i++) {
1553 reg = &table->regs[i];
1554 target = get_phy_target(reg->addr);
1555 if (target == compare) {
1556 *headline_idx = i;
1557 return 0;
1558 }
1559 }
1560
1561 /* case 2: RFE match, CV don't care */
1562 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE);
1563 for (i = 0; i < *headline_size; i++) {
1564 reg = &table->regs[i];
1565 target = get_phy_target(reg->addr);
1566 if (target == compare) {
1567 *headline_idx = i;
1568 return 0;
1569 }
1570 }
1571
1572 /* case 3: RFE match, CV max in table */
1573 for (i = 0; i < *headline_size; i++) {
1574 reg = &table->regs[i];
1575 rfe_para = get_phy_cond_rfe(reg->addr);
1576 cv_para = get_phy_cond_cv(reg->addr);
1577 if (rfe_para == rfe) {
1578 if (cv_para >= cv_max) {
1579 cv_max = cv_para;
1580 *headline_idx = i;
1581 case_matched = true;
1582 }
1583 }
1584 }
1585
1586 if (case_matched)
1587 return 0;
1588
1589 /* case 4: RFE don't care, CV max in table */
1590 for (i = 0; i < *headline_size; i++) {
1591 reg = &table->regs[i];
1592 rfe_para = get_phy_cond_rfe(reg->addr);
1593 cv_para = get_phy_cond_cv(reg->addr);
1594 if (rfe_para == PHY_COND_DONT_CARE) {
1595 if (cv_para >= cv_max) {
1596 cv_max = cv_para;
1597 *headline_idx = i;
1598 case_matched = true;
1599 }
1600 }
1601 }
1602
1603 if (case_matched)
1604 return 0;
1605
1606 return -EINVAL;
1607 }
1608
rtw89_phy_init_reg(struct rtw89_dev * rtwdev,const struct rtw89_phy_table * table,void (* config)(struct rtw89_dev * rtwdev,const struct rtw89_reg2_def * reg,enum rtw89_rf_path rf_path,void * data),void * extra_data)1609 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev,
1610 const struct rtw89_phy_table *table,
1611 void (*config)(struct rtw89_dev *rtwdev,
1612 const struct rtw89_reg2_def *reg,
1613 enum rtw89_rf_path rf_path,
1614 void *data),
1615 void *extra_data)
1616 {
1617 const struct rtw89_reg2_def *reg;
1618 enum rtw89_rf_path rf_path = table->rf_path;
1619 u8 rfe = rtwdev->efuse.rfe_type;
1620 u8 cv = rtwdev->hal.cv;
1621 u32 i;
1622 u32 headline_size = 0, headline_idx = 0;
1623 u32 target = 0, cfg_target;
1624 u8 cond;
1625 bool is_matched = true;
1626 bool target_found = false;
1627 int ret;
1628
1629 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size,
1630 &headline_idx, rfe, cv);
1631 if (ret) {
1632 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv);
1633 return;
1634 }
1635
1636 cfg_target = get_phy_target(table->regs[headline_idx].addr);
1637 for (i = headline_size; i < table->n_regs; i++) {
1638 reg = &table->regs[i];
1639 cond = get_phy_cond(reg->addr);
1640 switch (cond) {
1641 case PHY_COND_BRANCH_IF:
1642 case PHY_COND_BRANCH_ELIF:
1643 target = get_phy_target(reg->addr);
1644 break;
1645 case PHY_COND_BRANCH_ELSE:
1646 is_matched = false;
1647 if (!target_found) {
1648 rtw89_warn(rtwdev, "failed to load CR %x/%x\n",
1649 reg->addr, reg->data);
1650 return;
1651 }
1652 break;
1653 case PHY_COND_BRANCH_END:
1654 is_matched = true;
1655 target_found = false;
1656 break;
1657 case PHY_COND_CHECK:
1658 if (target_found) {
1659 is_matched = false;
1660 break;
1661 }
1662
1663 if (target == cfg_target) {
1664 is_matched = true;
1665 target_found = true;
1666 } else {
1667 is_matched = false;
1668 target_found = false;
1669 }
1670 break;
1671 default:
1672 if (is_matched)
1673 config(rtwdev, reg, rf_path, extra_data);
1674 break;
1675 }
1676 }
1677 }
1678
rtw89_phy_init_bb_reg(struct rtw89_dev * rtwdev)1679 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev)
1680 {
1681 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1682 const struct rtw89_chip_info *chip = rtwdev->chip;
1683 const struct rtw89_phy_table *bb_table;
1684 const struct rtw89_phy_table *bb_gain_table;
1685
1686 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table;
1687 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL);
1688 if (rtwdev->dbcc_en)
1689 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg,
1690 (void *)RTW89_PHY_1);
1691
1692 rtw89_chip_init_txpwr_unit(rtwdev);
1693
1694 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table;
1695 if (bb_gain_table)
1696 rtw89_phy_init_reg(rtwdev, bb_gain_table,
1697 chip->phy_def->config_bb_gain, NULL);
1698
1699 rtw89_phy_bb_reset(rtwdev);
1700 }
1701
rtw89_phy_nctl_poll(struct rtw89_dev * rtwdev)1702 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev)
1703 {
1704 rtw89_phy_write32(rtwdev, 0x8080, 0x4);
1705 udelay(1);
1706 return rtw89_phy_read32(rtwdev, 0x8080);
1707 }
1708
rtw89_phy_init_rf_reg(struct rtw89_dev * rtwdev,bool noio)1709 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio)
1710 {
1711 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
1712 enum rtw89_rf_path rf_path, void *data);
1713 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1714 const struct rtw89_chip_info *chip = rtwdev->chip;
1715 const struct rtw89_phy_table *rf_table;
1716 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info;
1717 u8 path;
1718
1719 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL);
1720 if (!rf_reg_info)
1721 return;
1722
1723 for (path = RF_PATH_A; path < chip->rf_path_num; path++) {
1724 rf_table = elm_info->rf_radio[path] ?
1725 elm_info->rf_radio[path] : chip->rf_table[path];
1726 rf_reg_info->rf_path = rf_table->rf_path;
1727 if (noio)
1728 config = rtw89_phy_config_rf_reg_noio;
1729 else
1730 config = rf_table->config ? rf_table->config :
1731 rtw89_phy_config_rf_reg;
1732 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info);
1733 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info))
1734 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n",
1735 rf_reg_info->rf_path);
1736 }
1737 kfree(rf_reg_info);
1738 }
1739
rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev * rtwdev)1740 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev)
1741 {
1742 const struct rtw89_chip_info *chip = rtwdev->chip;
1743 u32 val;
1744 int ret;
1745
1746 /* IQK/DPK clock & reset */
1747 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3);
1748 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1);
1749 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000);
1750 if (chip->chip_id != RTL8851B)
1751 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000);
1752 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT)
1753 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2);
1754
1755 /* check 0x8080 */
1756 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8);
1757
1758 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10,
1759 1000, false, rtwdev);
1760 if (ret)
1761 rtw89_err(rtwdev, "failed to poll nctl block\n");
1762 }
1763
rtw89_phy_init_rf_nctl(struct rtw89_dev * rtwdev)1764 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev)
1765 {
1766 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
1767 const struct rtw89_chip_info *chip = rtwdev->chip;
1768 const struct rtw89_phy_table *nctl_table;
1769
1770 rtw89_phy_preinit_rf_nctl(rtwdev);
1771
1772 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table;
1773 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL);
1774
1775 if (chip->nctl_post_table)
1776 rtw89_rfk_parser(rtwdev, chip->nctl_post_table);
1777 }
1778
rtw89_phy0_phy1_offset_ax(struct rtw89_dev * rtwdev,u32 addr)1779 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr)
1780 {
1781 u32 phy_page = addr >> 8;
1782 u32 ofst = 0;
1783
1784 switch (phy_page) {
1785 case 0x6:
1786 case 0x7:
1787 case 0x8:
1788 case 0x9:
1789 case 0xa:
1790 case 0xb:
1791 case 0xc:
1792 case 0xd:
1793 case 0x19:
1794 case 0x1a:
1795 case 0x1b:
1796 ofst = 0x2000;
1797 break;
1798 default:
1799 /* warning case */
1800 ofst = 0;
1801 break;
1802 }
1803
1804 if (phy_page >= 0x40 && phy_page <= 0x4f)
1805 ofst = 0x2000;
1806
1807 return ofst;
1808 }
1809
rtw89_phy_write32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data,enum rtw89_phy_idx phy_idx)1810 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1811 u32 data, enum rtw89_phy_idx phy_idx)
1812 {
1813 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1814 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1815 rtw89_phy_write32_mask(rtwdev, addr, mask, data);
1816 }
1817 EXPORT_SYMBOL(rtw89_phy_write32_idx);
1818
rtw89_phy_write32_idx_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1819 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1820 enum rtw89_phy_idx phy_idx)
1821 {
1822 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1823 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1824 rtw89_phy_write32_set(rtwdev, addr, bits);
1825 }
1826 EXPORT_SYMBOL(rtw89_phy_write32_idx_set);
1827
rtw89_phy_write32_idx_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits,enum rtw89_phy_idx phy_idx)1828 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1829 enum rtw89_phy_idx phy_idx)
1830 {
1831 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1832 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1833 rtw89_phy_write32_clr(rtwdev, addr, bits);
1834 }
1835 EXPORT_SYMBOL(rtw89_phy_write32_idx_clr);
1836
rtw89_phy_read32_idx(struct rtw89_dev * rtwdev,u32 addr,u32 mask,enum rtw89_phy_idx phy_idx)1837 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1838 enum rtw89_phy_idx phy_idx)
1839 {
1840 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1)
1841 addr += rtw89_phy0_phy1_offset(rtwdev, addr);
1842 return rtw89_phy_read32_mask(rtwdev, addr, mask);
1843 }
1844 EXPORT_SYMBOL(rtw89_phy_read32_idx);
1845
rtw89_phy_set_phy_regs(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 val)1846 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1847 u32 val)
1848 {
1849 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0);
1850
1851 if (!rtwdev->dbcc_en)
1852 return;
1853
1854 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1);
1855 }
1856 EXPORT_SYMBOL(rtw89_phy_set_phy_regs);
1857
rtw89_phy_write_reg3_tbl(struct rtw89_dev * rtwdev,const struct rtw89_phy_reg3_tbl * tbl)1858 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
1859 const struct rtw89_phy_reg3_tbl *tbl)
1860 {
1861 const struct rtw89_reg3_def *reg3;
1862 int i;
1863
1864 for (i = 0; i < tbl->size; i++) {
1865 reg3 = &tbl->reg3[i];
1866 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data);
1867 }
1868 }
1869 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl);
1870
rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev * rtwdev,u8 ant_gain_regd)1871 static u8 rtw89_phy_ant_gain_domain_to_regd(struct rtw89_dev *rtwdev, u8 ant_gain_regd)
1872 {
1873 switch (ant_gain_regd) {
1874 case RTW89_ANT_GAIN_ETSI:
1875 return RTW89_ETSI;
1876 default:
1877 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1878 "unknown antenna gain domain: %d\n",
1879 ant_gain_regd);
1880 return RTW89_REGD_NUM;
1881 }
1882 }
1883
1884 /* antenna gain in unit of 0.25 dbm */
1885 #define RTW89_ANT_GAIN_2GHZ_MIN -8
1886 #define RTW89_ANT_GAIN_2GHZ_MAX 14
1887 #define RTW89_ANT_GAIN_5GHZ_MIN -8
1888 #define RTW89_ANT_GAIN_5GHZ_MAX 20
1889 #define RTW89_ANT_GAIN_6GHZ_MIN -8
1890 #define RTW89_ANT_GAIN_6GHZ_MAX 20
1891
1892 #define RTW89_ANT_GAIN_REF_2GHZ 14
1893 #define RTW89_ANT_GAIN_REF_5GHZ 20
1894 #define RTW89_ANT_GAIN_REF_6GHZ 20
1895
rtw89_phy_ant_gain_init(struct rtw89_dev * rtwdev)1896 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev)
1897 {
1898 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
1899 const struct rtw89_chip_info *chip = rtwdev->chip;
1900 struct rtw89_acpi_rtag_result res = {};
1901 u32 domain;
1902 int ret;
1903 u8 i, j;
1904 u8 regd;
1905 u8 val;
1906
1907 if (!chip->support_ant_gain)
1908 return;
1909
1910 ret = rtw89_acpi_evaluate_rtag(rtwdev, &res);
1911 if (ret) {
1912 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1913 "acpi: cannot eval rtag: %d\n", ret);
1914 return;
1915 }
1916
1917 if (res.revision != 0) {
1918 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1919 "unknown rtag revision: %d\n", res.revision);
1920 return;
1921 }
1922
1923 domain = get_unaligned_le32(&res.domain);
1924
1925 for (i = 0; i < RTW89_ANT_GAIN_DOMAIN_NUM; i++) {
1926 if (!(domain & BIT(i)))
1927 continue;
1928
1929 regd = rtw89_phy_ant_gain_domain_to_regd(rtwdev, i);
1930 if (regd >= RTW89_REGD_NUM)
1931 continue;
1932 ant_gain->regd_enabled |= BIT(regd);
1933 }
1934
1935 for (i = 0; i < RTW89_ANT_GAIN_CHAIN_NUM; i++) {
1936 for (j = 0; j < RTW89_ANT_GAIN_SUBBAND_NR; j++) {
1937 val = res.ant_gain_table[i][j];
1938 switch (j) {
1939 default:
1940 case RTW89_ANT_GAIN_2GHZ_SUBBAND:
1941 val = RTW89_ANT_GAIN_REF_2GHZ -
1942 clamp_t(s8, val,
1943 RTW89_ANT_GAIN_2GHZ_MIN,
1944 RTW89_ANT_GAIN_2GHZ_MAX);
1945 break;
1946 case RTW89_ANT_GAIN_5GHZ_SUBBAND_1:
1947 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2:
1948 case RTW89_ANT_GAIN_5GHZ_SUBBAND_2E:
1949 case RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4:
1950 val = RTW89_ANT_GAIN_REF_5GHZ -
1951 clamp_t(s8, val,
1952 RTW89_ANT_GAIN_5GHZ_MIN,
1953 RTW89_ANT_GAIN_5GHZ_MAX);
1954 break;
1955 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L:
1956 case RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H:
1957 case RTW89_ANT_GAIN_6GHZ_SUBBAND_6:
1958 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L:
1959 case RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H:
1960 case RTW89_ANT_GAIN_6GHZ_SUBBAND_8:
1961 val = RTW89_ANT_GAIN_REF_6GHZ -
1962 clamp_t(s8, val,
1963 RTW89_ANT_GAIN_6GHZ_MIN,
1964 RTW89_ANT_GAIN_6GHZ_MAX);
1965 }
1966 ant_gain->offset[i][j] = val;
1967 }
1968 }
1969 }
1970
1971 static
rtw89_phy_ant_gain_get_subband(struct rtw89_dev * rtwdev,u32 center_freq)1972 enum rtw89_ant_gain_subband rtw89_phy_ant_gain_get_subband(struct rtw89_dev *rtwdev,
1973 u32 center_freq)
1974 {
1975 switch (center_freq) {
1976 default:
1977 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1978 "center freq: %u to antenna gain subband is unhandled\n",
1979 center_freq);
1980 fallthrough;
1981 case 2412 ... 2484:
1982 return RTW89_ANT_GAIN_2GHZ_SUBBAND;
1983 case 5180 ... 5240:
1984 return RTW89_ANT_GAIN_5GHZ_SUBBAND_1;
1985 case 5250 ... 5320:
1986 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2;
1987 case 5500 ... 5720:
1988 return RTW89_ANT_GAIN_5GHZ_SUBBAND_2E;
1989 case 5745 ... 5885:
1990 return RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4;
1991 case 5955 ... 6155:
1992 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L;
1993 case 6175 ... 6415:
1994 return RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H;
1995 case 6435 ... 6515:
1996 return RTW89_ANT_GAIN_6GHZ_SUBBAND_6;
1997 case 6535 ... 6695:
1998 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L;
1999 case 6715 ... 6855:
2000 return RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H;
2001
2002 /* freq 6875 (ch 185, 20MHz) spans RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H
2003 * and RTW89_ANT_GAIN_6GHZ_SUBBAND_8, so directly describe it with
2004 * struct rtw89_6ghz_span.
2005 */
2006
2007 case 6895 ... 7115:
2008 return RTW89_ANT_GAIN_6GHZ_SUBBAND_8;
2009 }
2010 }
2011
rtw89_phy_ant_gain_query(struct rtw89_dev * rtwdev,enum rtw89_rf_path path,u32 center_freq)2012 static s8 rtw89_phy_ant_gain_query(struct rtw89_dev *rtwdev,
2013 enum rtw89_rf_path path, u32 center_freq)
2014 {
2015 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2016 enum rtw89_ant_gain_subband subband_l, subband_h;
2017 const struct rtw89_6ghz_span *span;
2018
2019 span = rtw89_get_6ghz_span(rtwdev, center_freq);
2020
2021 if (span && RTW89_ANT_GAIN_SPAN_VALID(span)) {
2022 subband_l = span->ant_gain_subband_low;
2023 subband_h = span->ant_gain_subband_high;
2024 } else {
2025 subband_l = rtw89_phy_ant_gain_get_subband(rtwdev, center_freq);
2026 subband_h = subband_l;
2027 }
2028
2029 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2030 "center_freq %u: antenna gain subband {%u, %u}\n",
2031 center_freq, subband_l, subband_h);
2032
2033 return min(ant_gain->offset[path][subband_l],
2034 ant_gain->offset[path][subband_h]);
2035 }
2036
rtw89_phy_ant_gain_offset(struct rtw89_dev * rtwdev,u8 band,u32 center_freq)2037 static s8 rtw89_phy_ant_gain_offset(struct rtw89_dev *rtwdev, u8 band, u32 center_freq)
2038 {
2039 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2040 const struct rtw89_chip_info *chip = rtwdev->chip;
2041 u8 regd = rtw89_regd_get(rtwdev, band);
2042 s8 offset_patha, offset_pathb;
2043
2044 if (!chip->support_ant_gain)
2045 return 0;
2046
2047 if (!(ant_gain->regd_enabled & BIT(regd)))
2048 return 0;
2049
2050 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, center_freq);
2051 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, center_freq);
2052
2053 return max(offset_patha, offset_pathb);
2054 }
2055
rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2056 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
2057 const struct rtw89_chan *chan)
2058 {
2059 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2060 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
2061 s8 offset_patha, offset_pathb;
2062
2063 if (!(ant_gain->regd_enabled & BIT(regd)))
2064 return 0;
2065
2066 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2067 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2068
2069 return rtw89_phy_txpwr_rf_to_bb(rtwdev, offset_patha - offset_pathb);
2070 }
2071 EXPORT_SYMBOL(rtw89_phy_ant_gain_pwr_offset);
2072
rtw89_print_ant_gain(struct seq_file * m,struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2073 void rtw89_print_ant_gain(struct seq_file *m, struct rtw89_dev *rtwdev,
2074 const struct rtw89_chan *chan)
2075 {
2076 struct rtw89_ant_gain_info *ant_gain = &rtwdev->ant_gain;
2077 const struct rtw89_chip_info *chip = rtwdev->chip;
2078 u8 regd = rtw89_regd_get(rtwdev, chan->band_type);
2079 s8 offset_patha, offset_pathb;
2080
2081 if (!chip->support_ant_gain || !(ant_gain->regd_enabled & BIT(regd))) {
2082 seq_puts(m, "no DAG is applied\n");
2083 return;
2084 }
2085
2086 offset_patha = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_A, chan->freq);
2087 offset_pathb = rtw89_phy_ant_gain_query(rtwdev, RF_PATH_B, chan->freq);
2088
2089 seq_printf(m, "ChainA offset: %d dBm\n", offset_patha);
2090 seq_printf(m, "ChainB offset: %d dBm\n", offset_pathb);
2091 }
2092
2093 static const u8 rtw89_rs_idx_num_ax[] = {
2094 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM,
2095 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM,
2096 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX,
2097 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM,
2098 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX,
2099 };
2100
2101 static const u8 rtw89_rs_nss_num_ax[] = {
2102 [RTW89_RS_CCK] = 1,
2103 [RTW89_RS_OFDM] = 1,
2104 [RTW89_RS_MCS] = RTW89_NSS_NUM,
2105 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM,
2106 [RTW89_RS_OFFSET] = 1,
2107 };
2108
rtw89_phy_raw_byr_seek(struct rtw89_dev * rtwdev,struct rtw89_txpwr_byrate * head,const struct rtw89_rate_desc * desc)2109 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
2110 struct rtw89_txpwr_byrate *head,
2111 const struct rtw89_rate_desc *desc)
2112 {
2113 switch (desc->rs) {
2114 case RTW89_RS_CCK:
2115 return &head->cck[desc->idx];
2116 case RTW89_RS_OFDM:
2117 return &head->ofdm[desc->idx];
2118 case RTW89_RS_MCS:
2119 return &head->mcs[desc->ofdma][desc->nss][desc->idx];
2120 case RTW89_RS_HEDCM:
2121 return &head->hedcm[desc->ofdma][desc->nss][desc->idx];
2122 case RTW89_RS_OFFSET:
2123 return &head->offset[desc->idx];
2124 default:
2125 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs);
2126 return &head->trap;
2127 }
2128 }
2129
rtw89_phy_load_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_txpwr_table * tbl)2130 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
2131 const struct rtw89_txpwr_table *tbl)
2132 {
2133 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data;
2134 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size;
2135 struct rtw89_txpwr_byrate *byr_head;
2136 struct rtw89_rate_desc desc = {};
2137 s8 *byr;
2138 u32 data;
2139 u8 i;
2140
2141 for (; cfg < end; cfg++) {
2142 byr_head = &rtwdev->byr[cfg->band][0];
2143 desc.rs = cfg->rs;
2144 desc.nss = cfg->nss;
2145 data = cfg->data;
2146
2147 for (i = 0; i < cfg->len; i++, data >>= 8) {
2148 desc.idx = cfg->shf + i;
2149 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc);
2150 *byr = data & 0xff;
2151 }
2152 }
2153 }
2154 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate);
2155
rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)2156 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm)
2157 {
2158 const u8 tssi_deviation_point = 0;
2159 const u8 tssi_max_deviation = 2;
2160
2161 if (dbm <= tssi_deviation_point)
2162 dbm -= tssi_max_deviation;
2163
2164 return dbm;
2165 }
2166
rtw89_phy_get_tpe_constraint(struct rtw89_dev * rtwdev,u8 band)2167 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band)
2168 {
2169 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2170 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe;
2171 s8 cstr = S8_MAX;
2172
2173 if (band == RTW89_BAND_6G && tpe->valid)
2174 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint);
2175
2176 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr);
2177 }
2178
rtw89_phy_read_txpwr_byrate(struct rtw89_dev * rtwdev,u8 band,u8 bw,const struct rtw89_rate_desc * rate_desc)2179 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
2180 const struct rtw89_rate_desc *rate_desc)
2181 {
2182 struct rtw89_txpwr_byrate *byr_head;
2183 s8 *byr;
2184
2185 if (rate_desc->rs == RTW89_RS_CCK)
2186 band = RTW89_BAND_2G;
2187
2188 byr_head = &rtwdev->byr[band][bw];
2189 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc);
2190
2191 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr);
2192 }
2193
rtw89_channel_6g_to_idx(struct rtw89_dev * rtwdev,u8 channel_6g)2194 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g)
2195 {
2196 switch (channel_6g) {
2197 case 1 ... 29:
2198 return (channel_6g - 1) / 2;
2199 case 33 ... 61:
2200 return (channel_6g - 3) / 2;
2201 case 65 ... 93:
2202 return (channel_6g - 5) / 2;
2203 case 97 ... 125:
2204 return (channel_6g - 7) / 2;
2205 case 129 ... 157:
2206 return (channel_6g - 9) / 2;
2207 case 161 ... 189:
2208 return (channel_6g - 11) / 2;
2209 case 193 ... 221:
2210 return (channel_6g - 13) / 2;
2211 case 225 ... 253:
2212 return (channel_6g - 15) / 2;
2213 default:
2214 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g);
2215 return 0;
2216 }
2217 }
2218
rtw89_channel_to_idx(struct rtw89_dev * rtwdev,u8 band,u8 channel)2219 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel)
2220 {
2221 if (band == RTW89_BAND_6G)
2222 return rtw89_channel_6g_to_idx(rtwdev, channel);
2223
2224 switch (channel) {
2225 case 1 ... 14:
2226 return channel - 1;
2227 case 36 ... 64:
2228 return (channel - 36) / 2;
2229 case 100 ... 144:
2230 return ((channel - 100) / 2) + 15;
2231 case 149 ... 177:
2232 return ((channel - 149) / 2) + 38;
2233 default:
2234 rtw89_warn(rtwdev, "unknown channel: %d\n", channel);
2235 return 0;
2236 }
2237 }
2238
rtw89_phy_read_txpwr_limit(struct rtw89_dev * rtwdev,u8 band,u8 bw,u8 ntx,u8 rs,u8 bf,u8 ch)2239 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
2240 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch)
2241 {
2242 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2243 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2244 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2245 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2246 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2247 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2248 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2249 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2250 u8 regd = rtw89_regd_get(rtwdev, band);
2251 u8 reg6 = regulatory->reg_6ghz_power;
2252 s8 lmt = 0, sar, offset;
2253 s8 cstr;
2254
2255 switch (band) {
2256 case RTW89_BAND_2G:
2257 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2258 if (lmt)
2259 break;
2260
2261 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2262 break;
2263 case RTW89_BAND_5G:
2264 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx];
2265 if (lmt)
2266 break;
2267
2268 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx];
2269 break;
2270 case RTW89_BAND_6G:
2271 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx];
2272 if (lmt)
2273 break;
2274
2275 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW]
2276 [RTW89_REG_6GHZ_POWER_DFLT]
2277 [ch_idx];
2278 break;
2279 default:
2280 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2281 return 0;
2282 }
2283
2284 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq);
2285 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt + offset);
2286 sar = rtw89_query_sar(rtwdev, freq);
2287 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2288
2289 return min3(lmt, sar, cstr);
2290 }
2291 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit);
2292
2293 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \
2294 do { \
2295 u8 __i; \
2296 for (__i = 0; __i < RTW89_BF_NUM; __i++) \
2297 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \
2298 band, \
2299 bw, ntx, \
2300 rs, __i, \
2301 (ch)); \
2302 } while (0)
2303
rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch)2304 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev,
2305 struct rtw89_txpwr_limit_ax *lmt,
2306 u8 band, u8 ntx, u8 ch)
2307 {
2308 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2309 ntx, RTW89_RS_CCK, ch);
2310 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2311 ntx, RTW89_RS_CCK, ch);
2312 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2313 ntx, RTW89_RS_OFDM, ch);
2314 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2315 RTW89_CHANNEL_WIDTH_20,
2316 ntx, RTW89_RS_MCS, ch);
2317 }
2318
rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2319 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev,
2320 struct rtw89_txpwr_limit_ax *lmt,
2321 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2322 {
2323 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20,
2324 ntx, RTW89_RS_CCK, ch - 2);
2325 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40,
2326 ntx, RTW89_RS_CCK, ch);
2327 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2328 ntx, RTW89_RS_OFDM, pri_ch);
2329 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2330 RTW89_CHANNEL_WIDTH_20,
2331 ntx, RTW89_RS_MCS, ch - 2);
2332 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2333 RTW89_CHANNEL_WIDTH_20,
2334 ntx, RTW89_RS_MCS, ch + 2);
2335 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2336 RTW89_CHANNEL_WIDTH_40,
2337 ntx, RTW89_RS_MCS, ch);
2338 }
2339
rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2340 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev,
2341 struct rtw89_txpwr_limit_ax *lmt,
2342 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2343 {
2344 s8 val_0p5_n[RTW89_BF_NUM];
2345 s8 val_0p5_p[RTW89_BF_NUM];
2346 u8 i;
2347
2348 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2349 ntx, RTW89_RS_OFDM, pri_ch);
2350 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2351 RTW89_CHANNEL_WIDTH_20,
2352 ntx, RTW89_RS_MCS, ch - 6);
2353 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2354 RTW89_CHANNEL_WIDTH_20,
2355 ntx, RTW89_RS_MCS, ch - 2);
2356 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2357 RTW89_CHANNEL_WIDTH_20,
2358 ntx, RTW89_RS_MCS, ch + 2);
2359 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2360 RTW89_CHANNEL_WIDTH_20,
2361 ntx, RTW89_RS_MCS, ch + 6);
2362 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2363 RTW89_CHANNEL_WIDTH_40,
2364 ntx, RTW89_RS_MCS, ch - 4);
2365 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2366 RTW89_CHANNEL_WIDTH_40,
2367 ntx, RTW89_RS_MCS, ch + 4);
2368 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2369 RTW89_CHANNEL_WIDTH_80,
2370 ntx, RTW89_RS_MCS, ch);
2371
2372 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2373 ntx, RTW89_RS_MCS, ch - 4);
2374 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2375 ntx, RTW89_RS_MCS, ch + 4);
2376
2377 for (i = 0; i < RTW89_BF_NUM; i++)
2378 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2379 }
2380
rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ax * lmt,u8 band,u8 ntx,u8 ch,u8 pri_ch)2381 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev,
2382 struct rtw89_txpwr_limit_ax *lmt,
2383 u8 band, u8 ntx, u8 ch, u8 pri_ch)
2384 {
2385 s8 val_0p5_n[RTW89_BF_NUM];
2386 s8 val_0p5_p[RTW89_BF_NUM];
2387 s8 val_2p5_n[RTW89_BF_NUM];
2388 s8 val_2p5_p[RTW89_BF_NUM];
2389 u8 i;
2390
2391 /* fill ofdm section */
2392 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20,
2393 ntx, RTW89_RS_OFDM, pri_ch);
2394
2395 /* fill mcs 20m section */
2396 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band,
2397 RTW89_CHANNEL_WIDTH_20,
2398 ntx, RTW89_RS_MCS, ch - 14);
2399 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band,
2400 RTW89_CHANNEL_WIDTH_20,
2401 ntx, RTW89_RS_MCS, ch - 10);
2402 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band,
2403 RTW89_CHANNEL_WIDTH_20,
2404 ntx, RTW89_RS_MCS, ch - 6);
2405 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band,
2406 RTW89_CHANNEL_WIDTH_20,
2407 ntx, RTW89_RS_MCS, ch - 2);
2408 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band,
2409 RTW89_CHANNEL_WIDTH_20,
2410 ntx, RTW89_RS_MCS, ch + 2);
2411 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band,
2412 RTW89_CHANNEL_WIDTH_20,
2413 ntx, RTW89_RS_MCS, ch + 6);
2414 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band,
2415 RTW89_CHANNEL_WIDTH_20,
2416 ntx, RTW89_RS_MCS, ch + 10);
2417 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band,
2418 RTW89_CHANNEL_WIDTH_20,
2419 ntx, RTW89_RS_MCS, ch + 14);
2420
2421 /* fill mcs 40m section */
2422 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band,
2423 RTW89_CHANNEL_WIDTH_40,
2424 ntx, RTW89_RS_MCS, ch - 12);
2425 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band,
2426 RTW89_CHANNEL_WIDTH_40,
2427 ntx, RTW89_RS_MCS, ch - 4);
2428 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band,
2429 RTW89_CHANNEL_WIDTH_40,
2430 ntx, RTW89_RS_MCS, ch + 4);
2431 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band,
2432 RTW89_CHANNEL_WIDTH_40,
2433 ntx, RTW89_RS_MCS, ch + 12);
2434
2435 /* fill mcs 80m section */
2436 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band,
2437 RTW89_CHANNEL_WIDTH_80,
2438 ntx, RTW89_RS_MCS, ch - 8);
2439 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band,
2440 RTW89_CHANNEL_WIDTH_80,
2441 ntx, RTW89_RS_MCS, ch + 8);
2442
2443 /* fill mcs 160m section */
2444 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band,
2445 RTW89_CHANNEL_WIDTH_160,
2446 ntx, RTW89_RS_MCS, ch);
2447
2448 /* fill mcs 40m 0p5 section */
2449 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40,
2450 ntx, RTW89_RS_MCS, ch - 4);
2451 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40,
2452 ntx, RTW89_RS_MCS, ch + 4);
2453
2454 for (i = 0; i < RTW89_BF_NUM; i++)
2455 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]);
2456
2457 /* fill mcs 40m 2p5 section */
2458 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40,
2459 ntx, RTW89_RS_MCS, ch - 8);
2460 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40,
2461 ntx, RTW89_RS_MCS, ch + 8);
2462
2463 for (i = 0; i < RTW89_BF_NUM; i++)
2464 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]);
2465 }
2466
2467 static
rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ax * lmt,u8 ntx)2468 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2469 const struct rtw89_chan *chan,
2470 struct rtw89_txpwr_limit_ax *lmt,
2471 u8 ntx)
2472 {
2473 u8 band = chan->band_type;
2474 u8 pri_ch = chan->primary_channel;
2475 u8 ch = chan->channel;
2476 u8 bw = chan->band_width;
2477
2478 memset(lmt, 0, sizeof(*lmt));
2479
2480 switch (bw) {
2481 case RTW89_CHANNEL_WIDTH_20:
2482 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch);
2483 break;
2484 case RTW89_CHANNEL_WIDTH_40:
2485 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch,
2486 pri_ch);
2487 break;
2488 case RTW89_CHANNEL_WIDTH_80:
2489 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch,
2490 pri_ch);
2491 break;
2492 case RTW89_CHANNEL_WIDTH_160:
2493 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch,
2494 pri_ch);
2495 break;
2496 }
2497 }
2498
rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev * rtwdev,u8 band,u8 ru,u8 ntx,u8 ch)2499 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
2500 u8 ru, u8 ntx, u8 ch)
2501 {
2502 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms;
2503 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz;
2504 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz;
2505 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz;
2506 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory;
2507 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band);
2508 u32 freq = ieee80211_channel_to_frequency(ch, nl_band);
2509 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch);
2510 u8 regd = rtw89_regd_get(rtwdev, band);
2511 u8 reg6 = regulatory->reg_6ghz_power;
2512 s8 lmt_ru = 0, sar, offset;
2513 s8 cstr;
2514
2515 switch (band) {
2516 case RTW89_BAND_2G:
2517 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2518 if (lmt_ru)
2519 break;
2520
2521 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2522 break;
2523 case RTW89_BAND_5G:
2524 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx];
2525 if (lmt_ru)
2526 break;
2527
2528 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx];
2529 break;
2530 case RTW89_BAND_6G:
2531 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx];
2532 if (lmt_ru)
2533 break;
2534
2535 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW]
2536 [RTW89_REG_6GHZ_POWER_DFLT]
2537 [ch_idx];
2538 break;
2539 default:
2540 rtw89_warn(rtwdev, "unknown band type: %d\n", band);
2541 return 0;
2542 }
2543
2544 offset = rtw89_phy_ant_gain_offset(rtwdev, band, freq);
2545 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru + offset);
2546 sar = rtw89_query_sar(rtwdev, freq);
2547 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band);
2548
2549 return min3(lmt_ru, sar, cstr);
2550 }
2551
2552 static void
rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2553 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev,
2554 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2555 u8 band, u8 ntx, u8 ch)
2556 {
2557 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2558 RTW89_RU26,
2559 ntx, ch);
2560 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2561 RTW89_RU52,
2562 ntx, ch);
2563 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2564 RTW89_RU106,
2565 ntx, ch);
2566 }
2567
2568 static void
rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2569 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev,
2570 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2571 u8 band, u8 ntx, u8 ch)
2572 {
2573 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2574 RTW89_RU26,
2575 ntx, ch - 2);
2576 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2577 RTW89_RU26,
2578 ntx, ch + 2);
2579 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2580 RTW89_RU52,
2581 ntx, ch - 2);
2582 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2583 RTW89_RU52,
2584 ntx, ch + 2);
2585 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2586 RTW89_RU106,
2587 ntx, ch - 2);
2588 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2589 RTW89_RU106,
2590 ntx, ch + 2);
2591 }
2592
2593 static void
rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2594 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev,
2595 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2596 u8 band, u8 ntx, u8 ch)
2597 {
2598 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2599 RTW89_RU26,
2600 ntx, ch - 6);
2601 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2602 RTW89_RU26,
2603 ntx, ch - 2);
2604 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2605 RTW89_RU26,
2606 ntx, ch + 2);
2607 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2608 RTW89_RU26,
2609 ntx, ch + 6);
2610 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2611 RTW89_RU52,
2612 ntx, ch - 6);
2613 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2614 RTW89_RU52,
2615 ntx, ch - 2);
2616 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2617 RTW89_RU52,
2618 ntx, ch + 2);
2619 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2620 RTW89_RU52,
2621 ntx, ch + 6);
2622 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2623 RTW89_RU106,
2624 ntx, ch - 6);
2625 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2626 RTW89_RU106,
2627 ntx, ch - 2);
2628 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2629 RTW89_RU106,
2630 ntx, ch + 2);
2631 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2632 RTW89_RU106,
2633 ntx, ch + 6);
2634 }
2635
2636 static void
rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev * rtwdev,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 band,u8 ntx,u8 ch)2637 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev,
2638 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2639 u8 band, u8 ntx, u8 ch)
2640 {
2641 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 };
2642 int i;
2643
2644 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX);
2645 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) {
2646 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2647 RTW89_RU26,
2648 ntx,
2649 ch + ofst[i]);
2650 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2651 RTW89_RU52,
2652 ntx,
2653 ch + ofst[i]);
2654 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band,
2655 RTW89_RU106,
2656 ntx,
2657 ch + ofst[i]);
2658 }
2659 }
2660
2661 static
rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,struct rtw89_txpwr_limit_ru_ax * lmt_ru,u8 ntx)2662 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2663 const struct rtw89_chan *chan,
2664 struct rtw89_txpwr_limit_ru_ax *lmt_ru,
2665 u8 ntx)
2666 {
2667 u8 band = chan->band_type;
2668 u8 ch = chan->channel;
2669 u8 bw = chan->band_width;
2670
2671 memset(lmt_ru, 0, sizeof(*lmt_ru));
2672
2673 switch (bw) {
2674 case RTW89_CHANNEL_WIDTH_20:
2675 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx,
2676 ch);
2677 break;
2678 case RTW89_CHANNEL_WIDTH_40:
2679 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx,
2680 ch);
2681 break;
2682 case RTW89_CHANNEL_WIDTH_80:
2683 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx,
2684 ch);
2685 break;
2686 case RTW89_CHANNEL_WIDTH_160:
2687 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx,
2688 ch);
2689 break;
2690 }
2691 }
2692
rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2693 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev,
2694 const struct rtw89_chan *chan,
2695 enum rtw89_phy_idx phy_idx)
2696 {
2697 u8 max_nss_num = rtwdev->chip->rf_path_num;
2698 static const u8 rs[] = {
2699 RTW89_RS_CCK,
2700 RTW89_RS_OFDM,
2701 RTW89_RS_MCS,
2702 RTW89_RS_HEDCM,
2703 };
2704 struct rtw89_rate_desc cur = {};
2705 u8 band = chan->band_type;
2706 u8 ch = chan->channel;
2707 u32 addr, val;
2708 s8 v[4] = {};
2709 u8 i;
2710
2711 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2712 "[TXPWR] set txpwr byrate with ch=%d\n", ch);
2713
2714 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4);
2715 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4);
2716 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4);
2717 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4);
2718
2719 addr = R_AX_PWR_BY_RATE;
2720 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) {
2721 for (i = 0; i < ARRAY_SIZE(rs); i++) {
2722 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]])
2723 continue;
2724
2725 cur.rs = rs[i];
2726 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]];
2727 cur.idx++) {
2728 v[cur.idx % 4] =
2729 rtw89_phy_read_txpwr_byrate(rtwdev,
2730 band, 0,
2731 &cur);
2732
2733 if ((cur.idx + 1) % 4)
2734 continue;
2735
2736 val = FIELD_PREP(GENMASK(7, 0), v[0]) |
2737 FIELD_PREP(GENMASK(15, 8), v[1]) |
2738 FIELD_PREP(GENMASK(23, 16), v[2]) |
2739 FIELD_PREP(GENMASK(31, 24), v[3]);
2740
2741 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr,
2742 val);
2743 addr += 4;
2744 }
2745 }
2746 }
2747 }
2748
2749 static
rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2750 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev,
2751 const struct rtw89_chan *chan,
2752 enum rtw89_phy_idx phy_idx)
2753 {
2754 struct rtw89_rate_desc desc = {
2755 .nss = RTW89_NSS_1,
2756 .rs = RTW89_RS_OFFSET,
2757 };
2758 u8 band = chan->band_type;
2759 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {};
2760 u32 val;
2761
2762 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n");
2763
2764 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++)
2765 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc);
2766
2767 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5);
2768 val = FIELD_PREP(GENMASK(3, 0), v[0]) |
2769 FIELD_PREP(GENMASK(7, 4), v[1]) |
2770 FIELD_PREP(GENMASK(11, 8), v[2]) |
2771 FIELD_PREP(GENMASK(15, 12), v[3]) |
2772 FIELD_PREP(GENMASK(19, 16), v[4]);
2773
2774 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL,
2775 GENMASK(19, 0), val);
2776 }
2777
rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2778 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev,
2779 const struct rtw89_chan *chan,
2780 enum rtw89_phy_idx phy_idx)
2781 {
2782 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2783 struct rtw89_txpwr_limit_ax lmt;
2784 u8 ch = chan->channel;
2785 u8 bw = chan->band_width;
2786 const s8 *ptr;
2787 u32 addr, val;
2788 u8 i, j;
2789
2790 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2791 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw);
2792
2793 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) !=
2794 RTW89_TXPWR_LMT_PAGE_SIZE_AX);
2795
2796 addr = R_AX_PWR_LMT;
2797 for (i = 0; i < max_ntx_num; i++) {
2798 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i);
2799
2800 ptr = (s8 *)&lmt;
2801 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX;
2802 j += 4, addr += 4, ptr += 4) {
2803 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2804 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2805 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2806 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2807
2808 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2809 }
2810 }
2811 }
2812
rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)2813 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev,
2814 const struct rtw89_chan *chan,
2815 enum rtw89_phy_idx phy_idx)
2816 {
2817 u8 max_ntx_num = rtwdev->chip->rf_path_num;
2818 struct rtw89_txpwr_limit_ru_ax lmt_ru;
2819 u8 ch = chan->channel;
2820 u8 bw = chan->band_width;
2821 const s8 *ptr;
2822 u32 addr, val;
2823 u8 i, j;
2824
2825 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
2826 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw);
2827
2828 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) !=
2829 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX);
2830
2831 addr = R_AX_PWR_RU_LMT;
2832 for (i = 0; i < max_ntx_num; i++) {
2833 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i);
2834
2835 ptr = (s8 *)&lmt_ru;
2836 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX;
2837 j += 4, addr += 4, ptr += 4) {
2838 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) |
2839 FIELD_PREP(GENMASK(15, 8), ptr[1]) |
2840 FIELD_PREP(GENMASK(23, 16), ptr[2]) |
2841 FIELD_PREP(GENMASK(31, 24), ptr[3]);
2842
2843 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val);
2844 }
2845 }
2846 }
2847
2848 struct rtw89_phy_iter_ra_data {
2849 struct rtw89_dev *rtwdev;
2850 struct sk_buff *c2h;
2851 };
2852
__rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link * rtwsta_link,struct ieee80211_link_sta * link_sta,struct rtw89_phy_iter_ra_data * ra_data)2853 static void __rtw89_phy_c2h_ra_rpt_iter(struct rtw89_sta_link *rtwsta_link,
2854 struct ieee80211_link_sta *link_sta,
2855 struct rtw89_phy_iter_ra_data *ra_data)
2856 {
2857 struct rtw89_dev *rtwdev = ra_data->rtwdev;
2858 const struct rtw89_c2h_ra_rpt *c2h =
2859 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data;
2860 struct rtw89_ra_report *ra_report = &rtwsta_link->ra_report;
2861 const struct rtw89_chip_info *chip = rtwdev->chip;
2862 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE;
2863 u8 mode, rate, bw, giltf, mac_id;
2864 u16 legacy_bitrate;
2865 bool valid;
2866 u8 mcs = 0;
2867 u8 t;
2868
2869 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID);
2870 if (mac_id != rtwsta_link->mac_id)
2871 return;
2872
2873 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS);
2874 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW);
2875 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF);
2876 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL);
2877
2878 if (format_v1) {
2879 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7);
2880 rate |= u8_encode_bits(t, BIT(7));
2881 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2);
2882 bw |= u8_encode_bits(t, BIT(2));
2883 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2);
2884 mode |= u8_encode_bits(t, BIT(2));
2885 }
2886
2887 if (mode == RTW89_RA_RPT_MODE_LEGACY) {
2888 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate);
2889 if (!valid)
2890 return;
2891 }
2892
2893 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate));
2894
2895 switch (mode) {
2896 case RTW89_RA_RPT_MODE_LEGACY:
2897 ra_report->txrate.legacy = legacy_bitrate;
2898 break;
2899 case RTW89_RA_RPT_MODE_HT:
2900 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS;
2901 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw))
2902 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate),
2903 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate));
2904 else
2905 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate);
2906 ra_report->txrate.mcs = rate;
2907 if (giltf)
2908 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2909 mcs = ra_report->txrate.mcs & 0x07;
2910 break;
2911 case RTW89_RA_RPT_MODE_VHT:
2912 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS;
2913 ra_report->txrate.mcs = format_v1 ?
2914 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2915 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2916 ra_report->txrate.nss = format_v1 ?
2917 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2918 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2919 if (giltf)
2920 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
2921 mcs = ra_report->txrate.mcs;
2922 break;
2923 case RTW89_RA_RPT_MODE_HE:
2924 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS;
2925 ra_report->txrate.mcs = format_v1 ?
2926 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) :
2927 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS);
2928 ra_report->txrate.nss = format_v1 ?
2929 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 :
2930 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1;
2931 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2932 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8;
2933 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2934 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6;
2935 else
2936 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2;
2937 mcs = ra_report->txrate.mcs;
2938 break;
2939 case RTW89_RA_RPT_MODE_EHT:
2940 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS;
2941 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1);
2942 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1;
2943 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08)
2944 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8;
2945 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16)
2946 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6;
2947 else
2948 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2;
2949 mcs = ra_report->txrate.mcs;
2950 break;
2951 }
2952
2953 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw);
2954 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate);
2955 ra_report->hw_rate = format_v1 ?
2956 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) |
2957 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) :
2958 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) |
2959 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL);
2960 ra_report->might_fallback_legacy = mcs <= 2;
2961 link_sta->agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report);
2962 rtwsta_link->max_agg_wait = link_sta->agg.max_rc_amsdu_len / 1500 - 1;
2963 }
2964
rtw89_phy_c2h_ra_rpt_iter(void * data,struct ieee80211_sta * sta)2965 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta)
2966 {
2967 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data;
2968 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
2969 struct rtw89_sta_link *rtwsta_link;
2970 struct ieee80211_link_sta *link_sta;
2971 unsigned int link_id;
2972
2973 rcu_read_lock();
2974
2975 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
2976 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
2977 __rtw89_phy_c2h_ra_rpt_iter(rtwsta_link, link_sta, ra_data);
2978 }
2979
2980 rcu_read_unlock();
2981 }
2982
2983 static void
rtw89_phy_c2h_ra_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)2984 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
2985 {
2986 struct rtw89_phy_iter_ra_data ra_data;
2987
2988 ra_data.rtwdev = rtwdev;
2989 ra_data.c2h = c2h;
2990 ieee80211_iterate_stations_atomic(rtwdev->hw,
2991 rtw89_phy_c2h_ra_rpt_iter,
2992 &ra_data);
2993 }
2994
2995 static
2996 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev,
2997 struct sk_buff *c2h, u32 len) = {
2998 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt,
2999 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL,
3000 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL,
3001 };
3002
rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3003 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev,
3004 enum rtw89_phy_c2h_rfk_log_func func,
3005 void *content, u16 len)
3006 {
3007 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk;
3008 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck;
3009 struct rtw89_c2h_rf_dack_rpt_log *dack;
3010 struct rtw89_c2h_rf_tssi_rpt_log *tssi;
3011 struct rtw89_c2h_rf_dpk_rpt_log *dpk;
3012 struct rtw89_c2h_rf_iqk_rpt_log *iqk;
3013 int i, j, k;
3014
3015 switch (func) {
3016 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3017 if (len != sizeof(*iqk))
3018 goto out;
3019
3020 iqk = content;
3021 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3022 "[IQK] iqk->is_iqk_init = %x\n", iqk->is_iqk_init);
3023 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3024 "[IQK] iqk->is_reload = %x\n", iqk->is_reload);
3025 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3026 "[IQK] iqk->is_nbiqk = %x\n", iqk->is_nbiqk);
3027 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3028 "[IQK] iqk->txiqk_en = %x\n", iqk->txiqk_en);
3029 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3030 "[IQK] iqk->rxiqk_en = %x\n", iqk->rxiqk_en);
3031 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3032 "[IQK] iqk->lok_en = %x\n", iqk->lok_en);
3033 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3034 "[IQK] iqk->iqk_xym_en = %x\n", iqk->iqk_xym_en);
3035 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3036 "[IQK] iqk->iqk_sram_en = %x\n", iqk->iqk_sram_en);
3037 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3038 "[IQK] iqk->iqk_fft_en = %x\n", iqk->iqk_fft_en);
3039 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3040 "[IQK] iqk->is_fw_iqk = %x\n", iqk->is_fw_iqk);
3041 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3042 "[IQK] iqk->is_iqk_enable = %x\n", iqk->is_iqk_enable);
3043 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3044 "[IQK] iqk->iqk_cfir_en = %x\n", iqk->iqk_cfir_en);
3045 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3046 "[IQK] iqk->thermal_rek_en = %x\n", iqk->thermal_rek_en);
3047 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3048 "[IQK] iqk->version = %x\n", iqk->version);
3049 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3050 "[IQK] iqk->phy = %x\n", iqk->phy);
3051 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3052 "[IQK] iqk->fwk_status = %x\n", iqk->fwk_status);
3053
3054 for (i = 0; i < 2; i++) {
3055 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3056 "[IQK] ======== Path %x ========\n", i);
3057 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_band[%d] = %x\n",
3058 i, iqk->iqk_band[i]);
3059 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_ch[%d] = %x\n",
3060 i, iqk->iqk_ch[i]);
3061 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_bw[%d] = %x\n",
3062 i, iqk->iqk_bw[i]);
3063 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_idac[%d] = %x\n",
3064 i, le32_to_cpu(iqk->lok_idac[i]));
3065 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->lok_vbuf[%d] = %x\n",
3066 i, le32_to_cpu(iqk->lok_vbuf[i]));
3067 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_tx_fail[%d] = %x\n",
3068 i, iqk->iqk_tx_fail[i]);
3069 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[IQK] iqk->iqk_rx_fail[%d] = %x\n",
3070 i, iqk->iqk_rx_fail[i]);
3071 for (j = 0; j < 4; j++)
3072 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3073 "[IQK] iqk->rftxgain[%d][%d] = %x\n",
3074 i, j, le32_to_cpu(iqk->rftxgain[i][j]));
3075 for (j = 0; j < 4; j++)
3076 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3077 "[IQK] iqk->tx_xym[%d][%d] = %x\n",
3078 i, j, le32_to_cpu(iqk->tx_xym[i][j]));
3079 for (j = 0; j < 4; j++)
3080 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3081 "[IQK] iqk->rfrxgain[%d][%d] = %x\n",
3082 i, j, le32_to_cpu(iqk->rfrxgain[i][j]));
3083 for (j = 0; j < 4; j++)
3084 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3085 "[IQK] iqk->rx_xym[%d][%d] = %x\n",
3086 i, j, le32_to_cpu(iqk->rx_xym[i][j]));
3087 }
3088 return;
3089 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3090 if (len != sizeof(*dpk))
3091 goto out;
3092
3093 dpk = content;
3094 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3095 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n",
3096 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok);
3097 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3098 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n",
3099 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q);
3100 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3101 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n",
3102 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov);
3103 return;
3104 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3105 if (len != sizeof(*dack))
3106 goto out;
3107
3108 dack = content;
3109
3110 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]FWDACK SUMMARY!!!!!\n");
3111 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3112 "[DACK]FWDACK ver = 0x%x, FWDACK rpt_ver = 0x%x, driver rpt_ver = 0x%x\n",
3113 dack->fwdack_ver, dack->fwdack_info_ver, 0x2);
3114
3115 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3116 "[DACK]timeout code = [0x%x 0x%x 0x%x 0x%x 0x%x]\n",
3117 dack->addck_timeout, dack->cdack_timeout, dack->dadck_timeout,
3118 dack->adgaink_timeout, dack->msbk_timeout);
3119 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3120 "[DACK]DACK fail = 0x%x\n", dack->dack_fail);
3121 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3122 "[DACK]S0 WBADCK = [0x%x]\n", dack->wbdck_d[0]);
3123 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3124 "[DACK]S1 WBADCK = [0x%x]\n", dack->wbdck_d[1]);
3125 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3126 "[DACK]DRCK = [0x%x]\n", dack->rck_d);
3127 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n",
3128 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]);
3129 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n",
3130 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]);
3131 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n",
3132 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]);
3133 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n",
3134 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]);
3135
3136 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n",
3137 ((u32)dack->addck2_hd[0][0][0] << 8) | dack->addck2_ld[0][0][0],
3138 ((u32)dack->addck2_hd[0][0][1] << 8) | dack->addck2_ld[0][0][1]);
3139 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n",
3140 ((u32)dack->addck2_hd[0][1][0] << 8) | dack->addck2_ld[0][1][0],
3141 ((u32)dack->addck2_hd[0][1][1] << 8) | dack->addck2_ld[0][1][1]);
3142 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n",
3143 ((u32)dack->addck2_hd[1][0][0] << 8) | dack->addck2_ld[1][0][0],
3144 ((u32)dack->addck2_hd[1][0][1] << 8) | dack->addck2_ld[1][0][1]);
3145 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n",
3146 ((u32)dack->addck2_hd[1][1][0] << 8) | dack->addck2_ld[1][1][0],
3147 ((u32)dack->addck2_hd[1][1][1] << 8) | dack->addck2_ld[1][1][1]);
3148
3149 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3150 dack->adgaink_d[0][0], dack->adgaink_d[0][1]);
3151 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n",
3152 dack->adgaink_d[1][0], dack->adgaink_d[1][1]);
3153
3154 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3155 dack->dadck_d[0][0], dack->dadck_d[0][1]);
3156 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n",
3157 dack->dadck_d[1][0], dack->dadck_d[1][1]);
3158
3159 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n",
3160 ((u32)dack->biask_hd[0][0] << 8) | dack->biask_ld[0][0]);
3161 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n",
3162 ((u32)dack->biask_hd[1][0] << 8) | dack->biask_ld[1][0]);
3163
3164 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic:\n");
3165 for (i = 0; i < 0x10; i++)
3166 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3167 dack->msbk_d[0][0][i]);
3168
3169 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc:\n");
3170 for (i = 0; i < 0x10; i++)
3171 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3172 dack->msbk_d[0][1][i]);
3173
3174 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic:\n");
3175 for (i = 0; i < 0x10; i++)
3176 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3177 dack->msbk_d[1][0][i]);
3178
3179 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc:\n");
3180 for (i = 0; i < 0x10; i++)
3181 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x\n",
3182 dack->msbk_d[1][1][i]);
3183 return;
3184 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3185 if (len != sizeof(*rxdck))
3186 goto out;
3187
3188 rxdck = content;
3189 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3190 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n",
3191 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch,
3192 rxdck->timeout);
3193 return;
3194 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3195 if (len != sizeof(*tssi))
3196 goto out;
3197
3198 tssi = content;
3199 for (i = 0; i < 2; i++) {
3200 for (j = 0; j < 2; j++) {
3201 for (k = 0; k < 4; k++) {
3202 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3203 "[TSSI] alignment_power_cw_h[%d][%d][%d]=%d\n",
3204 i, j, k, tssi->alignment_power_cw_h[i][j][k]);
3205 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3206 "[TSSI] alignment_power_cw_l[%d][%d][%d]=%d\n",
3207 i, j, k, tssi->alignment_power_cw_l[i][j][k]);
3208 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3209 "[TSSI] alignment_power[%d][%d][%d]=%d\n",
3210 i, j, k, tssi->alignment_power[i][j][k]);
3211 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3212 "[TSSI] alignment_power_cw[%d][%d][%d]=%d\n",
3213 i, j, k,
3214 (tssi->alignment_power_cw_h[i][j][k] << 8) +
3215 tssi->alignment_power_cw_l[i][j][k]);
3216 }
3217
3218 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3219 "[TSSI] tssi_alimk_state[%d][%d]=%d\n",
3220 i, j, tssi->tssi_alimk_state[i][j]);
3221 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3222 "[TSSI] default_txagc_offset[%d]=%d\n",
3223 j, tssi->default_txagc_offset[0][j]);
3224 }
3225 }
3226 return;
3227 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3228 if (len != sizeof(*txgapk))
3229 goto out;
3230
3231 txgapk = content;
3232 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3233 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n",
3234 le32_to_cpu(txgapk->r0x8010[0]),
3235 le32_to_cpu(txgapk->r0x8010[1]));
3236 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n",
3237 txgapk->chk_id);
3238 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n",
3239 le32_to_cpu(txgapk->chk_cnt));
3240 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n",
3241 txgapk->ver);
3242 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n",
3243 txgapk->rsv1);
3244
3245 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n",
3246 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]);
3247 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n",
3248 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]);
3249 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n",
3250 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]);
3251 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n",
3252 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]);
3253 return;
3254 default:
3255 break;
3256 }
3257
3258 out:
3259 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3260 "unexpected RFK func %d report log with length %d\n", func, len);
3261 }
3262
rtw89_phy_c2h_rfk_run_log(struct rtw89_dev * rtwdev,enum rtw89_phy_c2h_rfk_log_func func,void * content,u16 len)3263 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev,
3264 enum rtw89_phy_c2h_rfk_log_func func,
3265 void *content, u16 len)
3266 {
3267 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info;
3268 const struct rtw89_c2h_rf_run_log *log = content;
3269 const struct rtw89_fw_element_hdr *elm;
3270 u32 fmt_idx;
3271 u16 offset;
3272
3273 if (sizeof(*log) != len)
3274 return false;
3275
3276 if (!elm_info->rfk_log_fmt)
3277 return false;
3278
3279 elm = elm_info->rfk_log_fmt->elm[func];
3280 fmt_idx = le32_to_cpu(log->fmt_idx);
3281 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr)
3282 return false;
3283
3284 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]);
3285 if (offset == 0)
3286 return false;
3287
3288 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset],
3289 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]),
3290 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3]));
3291
3292 return true;
3293 }
3294
rtw89_phy_c2h_rfk_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len,enum rtw89_phy_c2h_rfk_log_func func,const char * rfk_name)3295 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h,
3296 u32 len, enum rtw89_phy_c2h_rfk_log_func func,
3297 const char *rfk_name)
3298 {
3299 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data;
3300 struct rtw89_c2h_rf_log_hdr *log_hdr;
3301 void *log_ptr = c2h_hdr;
3302 u16 content_len;
3303 u16 chunk_len;
3304 bool handled;
3305
3306 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK))
3307 return;
3308
3309 log_ptr += sizeof(*c2h_hdr);
3310 len -= sizeof(*c2h_hdr);
3311
3312 while (len > sizeof(*log_hdr)) {
3313 log_hdr = log_ptr;
3314 content_len = le16_to_cpu(log_hdr->len);
3315 chunk_len = content_len + sizeof(*log_hdr);
3316
3317 if (chunk_len > len)
3318 break;
3319
3320 switch (log_hdr->type) {
3321 case RTW89_RF_RUN_LOG:
3322 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func,
3323 log_hdr->content, content_len);
3324 if (handled)
3325 break;
3326
3327 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n",
3328 rfk_name, content_len, log_hdr->content);
3329 break;
3330 case RTW89_RF_RPT_LOG:
3331 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func,
3332 log_hdr->content, content_len);
3333 break;
3334 default:
3335 return;
3336 }
3337
3338 log_ptr += chunk_len;
3339 len -= chunk_len;
3340 }
3341 }
3342
3343 static void
rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3344 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3345 {
3346 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3347 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK");
3348 }
3349
3350 static void
rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3351 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3352 {
3353 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3354 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK");
3355 }
3356
3357 static void
rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3358 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3359 {
3360 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3361 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK");
3362 }
3363
3364 static void
rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3365 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3366 {
3367 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3368 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK");
3369 }
3370
3371 static void
rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3372 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3373 {
3374 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3375 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI");
3376 }
3377
3378 static void
rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3379 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3380 {
3381 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len,
3382 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK");
3383 }
3384
3385 static
3386 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev,
3387 struct sk_buff *c2h, u32 len) = {
3388 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk,
3389 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk,
3390 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack,
3391 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck,
3392 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi,
3393 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk,
3394 };
3395
3396 static
rtw89_phy_rfk_report_prep(struct rtw89_dev * rtwdev)3397 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev)
3398 {
3399 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3400
3401 wait->state = RTW89_RFK_STATE_START;
3402 wait->start_time = ktime_get();
3403 reinit_completion(&wait->completion);
3404 }
3405
3406 static
rtw89_phy_rfk_report_wait(struct rtw89_dev * rtwdev,const char * rfk_name,unsigned int ms)3407 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name,
3408 unsigned int ms)
3409 {
3410 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3411 unsigned long time_left;
3412
3413 /* Since we can't receive C2H event during SER, use a fixed delay. */
3414 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) {
3415 fsleep(1000 * ms / 2);
3416 goto out;
3417 }
3418
3419 time_left = wait_for_completion_timeout(&wait->completion,
3420 msecs_to_jiffies(ms));
3421 if (time_left == 0) {
3422 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name);
3423 return -ETIMEDOUT;
3424 } else if (wait->state != RTW89_RFK_STATE_OK) {
3425 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n",
3426 rfk_name, wait->state);
3427 return -EFAULT;
3428 }
3429
3430 out:
3431 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n",
3432 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time));
3433
3434 return 0;
3435 }
3436
3437 static void
rtw89_phy_c2h_rfk_report_state(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3438 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3439 {
3440 const struct rtw89_c2h_rfk_report *report =
3441 (const struct rtw89_c2h_rfk_report *)c2h->data;
3442 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait;
3443
3444 wait->state = report->state;
3445 wait->version = report->version;
3446
3447 complete(&wait->completion);
3448
3449 rtw89_debug(rtwdev, RTW89_DBG_RFK,
3450 "RFK report state %d with version %d (%*ph)\n",
3451 wait->state, wait->version,
3452 (int)(len - sizeof(report->hdr)), &report->state);
3453 }
3454
3455 static void
rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)3456 rtw89_phy_c2h_rfk_log_tas_pwr(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len)
3457 {
3458 }
3459
3460 static
3461 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev,
3462 struct sk_buff *c2h, u32 len) = {
3463 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state,
3464 [RTW89_PHY_C2H_RFK_LOG_TAS_PWR] = rtw89_phy_c2h_rfk_log_tas_pwr,
3465 };
3466
rtw89_phy_c2h_chk_atomic(struct rtw89_dev * rtwdev,u8 class,u8 func)3467 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func)
3468 {
3469 switch (class) {
3470 case RTW89_PHY_C2H_RFK_LOG:
3471 switch (func) {
3472 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK:
3473 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK:
3474 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK:
3475 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK:
3476 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI:
3477 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK:
3478 return true;
3479 default:
3480 return false;
3481 }
3482 case RTW89_PHY_C2H_RFK_REPORT:
3483 switch (func) {
3484 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE:
3485 return true;
3486 default:
3487 return false;
3488 }
3489 default:
3490 return false;
3491 }
3492 }
3493
rtw89_phy_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)3494 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
3495 u32 len, u8 class, u8 func)
3496 {
3497 void (*handler)(struct rtw89_dev *rtwdev,
3498 struct sk_buff *c2h, u32 len) = NULL;
3499
3500 switch (class) {
3501 case RTW89_PHY_C2H_CLASS_RA:
3502 if (func < RTW89_PHY_C2H_FUNC_RA_MAX)
3503 handler = rtw89_phy_c2h_ra_handler[func];
3504 break;
3505 case RTW89_PHY_C2H_RFK_LOG:
3506 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler))
3507 handler = rtw89_phy_c2h_rfk_log_handler[func];
3508 break;
3509 case RTW89_PHY_C2H_RFK_REPORT:
3510 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler))
3511 handler = rtw89_phy_c2h_rfk_report_handler[func];
3512 break;
3513 case RTW89_PHY_C2H_CLASS_DM:
3514 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY)
3515 return;
3516 fallthrough;
3517 default:
3518 rtw89_info(rtwdev, "PHY c2h class %d not support\n", class);
3519 return;
3520 }
3521 if (!handler) {
3522 rtw89_info(rtwdev, "PHY c2h class %d func %d not support\n", class,
3523 func);
3524 return;
3525 }
3526 handler(rtwdev, skb, len);
3527 }
3528
rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,unsigned int ms)3529 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
3530 enum rtw89_phy_idx phy_idx,
3531 unsigned int ms)
3532 {
3533 int ret;
3534
3535 rtw89_phy_rfk_report_prep(rtwdev);
3536
3537 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx);
3538 if (ret)
3539 return ret;
3540
3541 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms);
3542 }
3543 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait);
3544
rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,enum rtw89_tssi_mode tssi_mode,unsigned int ms)3545 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
3546 enum rtw89_phy_idx phy_idx,
3547 const struct rtw89_chan *chan,
3548 enum rtw89_tssi_mode tssi_mode,
3549 unsigned int ms)
3550 {
3551 int ret;
3552
3553 rtw89_phy_rfk_report_prep(rtwdev);
3554
3555 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, chan, tssi_mode);
3556 if (ret)
3557 return ret;
3558
3559 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms);
3560 }
3561 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait);
3562
rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3563 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
3564 enum rtw89_phy_idx phy_idx,
3565 const struct rtw89_chan *chan,
3566 unsigned int ms)
3567 {
3568 int ret;
3569
3570 rtw89_phy_rfk_report_prep(rtwdev);
3571
3572 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx, chan);
3573 if (ret)
3574 return ret;
3575
3576 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms);
3577 }
3578 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait);
3579
rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3580 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
3581 enum rtw89_phy_idx phy_idx,
3582 const struct rtw89_chan *chan,
3583 unsigned int ms)
3584 {
3585 int ret;
3586
3587 rtw89_phy_rfk_report_prep(rtwdev);
3588
3589 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx, chan);
3590 if (ret)
3591 return ret;
3592
3593 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms);
3594 }
3595 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait);
3596
rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3597 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
3598 enum rtw89_phy_idx phy_idx,
3599 const struct rtw89_chan *chan,
3600 unsigned int ms)
3601 {
3602 int ret;
3603
3604 rtw89_phy_rfk_report_prep(rtwdev);
3605
3606 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx, chan);
3607 if (ret)
3608 return ret;
3609
3610 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms);
3611 }
3612 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait);
3613
rtw89_phy_rfk_dack_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,unsigned int ms)3614 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
3615 enum rtw89_phy_idx phy_idx,
3616 const struct rtw89_chan *chan,
3617 unsigned int ms)
3618 {
3619 int ret;
3620
3621 rtw89_phy_rfk_report_prep(rtwdev);
3622
3623 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx, chan);
3624 if (ret)
3625 return ret;
3626
3627 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms);
3628 }
3629 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait);
3630
rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,const struct rtw89_chan * chan,bool is_chl_k,unsigned int ms)3631 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
3632 enum rtw89_phy_idx phy_idx,
3633 const struct rtw89_chan *chan,
3634 bool is_chl_k, unsigned int ms)
3635 {
3636 int ret;
3637
3638 rtw89_phy_rfk_report_prep(rtwdev);
3639
3640 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx, chan, is_chl_k);
3641 if (ret)
3642 return ret;
3643
3644 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms);
3645 }
3646 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait);
3647
phy_tssi_get_cck_group(u8 ch)3648 static u32 phy_tssi_get_cck_group(u8 ch)
3649 {
3650 switch (ch) {
3651 case 1 ... 2:
3652 return 0;
3653 case 3 ... 5:
3654 return 1;
3655 case 6 ... 8:
3656 return 2;
3657 case 9 ... 11:
3658 return 3;
3659 case 12 ... 13:
3660 return 4;
3661 case 14:
3662 return 5;
3663 }
3664
3665 return 0;
3666 }
3667
3668 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31)
3669 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx))
3670 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT)
3671 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \
3672 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT)
3673 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \
3674 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1)
3675
phy_tssi_get_ofdm_group(u8 ch)3676 static u32 phy_tssi_get_ofdm_group(u8 ch)
3677 {
3678 switch (ch) {
3679 case 1 ... 2:
3680 return 0;
3681 case 3 ... 5:
3682 return 1;
3683 case 6 ... 8:
3684 return 2;
3685 case 9 ... 11:
3686 return 3;
3687 case 12 ... 14:
3688 return 4;
3689 case 36 ... 40:
3690 return 5;
3691 case 41 ... 43:
3692 return PHY_TSSI_EXTRA_GROUP(5);
3693 case 44 ... 48:
3694 return 6;
3695 case 49 ... 51:
3696 return PHY_TSSI_EXTRA_GROUP(6);
3697 case 52 ... 56:
3698 return 7;
3699 case 57 ... 59:
3700 return PHY_TSSI_EXTRA_GROUP(7);
3701 case 60 ... 64:
3702 return 8;
3703 case 100 ... 104:
3704 return 9;
3705 case 105 ... 107:
3706 return PHY_TSSI_EXTRA_GROUP(9);
3707 case 108 ... 112:
3708 return 10;
3709 case 113 ... 115:
3710 return PHY_TSSI_EXTRA_GROUP(10);
3711 case 116 ... 120:
3712 return 11;
3713 case 121 ... 123:
3714 return PHY_TSSI_EXTRA_GROUP(11);
3715 case 124 ... 128:
3716 return 12;
3717 case 129 ... 131:
3718 return PHY_TSSI_EXTRA_GROUP(12);
3719 case 132 ... 136:
3720 return 13;
3721 case 137 ... 139:
3722 return PHY_TSSI_EXTRA_GROUP(13);
3723 case 140 ... 144:
3724 return 14;
3725 case 149 ... 153:
3726 return 15;
3727 case 154 ... 156:
3728 return PHY_TSSI_EXTRA_GROUP(15);
3729 case 157 ... 161:
3730 return 16;
3731 case 162 ... 164:
3732 return PHY_TSSI_EXTRA_GROUP(16);
3733 case 165 ... 169:
3734 return 17;
3735 case 170 ... 172:
3736 return PHY_TSSI_EXTRA_GROUP(17);
3737 case 173 ... 177:
3738 return 18;
3739 }
3740
3741 return 0;
3742 }
3743
phy_tssi_get_6g_ofdm_group(u8 ch)3744 static u32 phy_tssi_get_6g_ofdm_group(u8 ch)
3745 {
3746 switch (ch) {
3747 case 1 ... 5:
3748 return 0;
3749 case 6 ... 8:
3750 return PHY_TSSI_EXTRA_GROUP(0);
3751 case 9 ... 13:
3752 return 1;
3753 case 14 ... 16:
3754 return PHY_TSSI_EXTRA_GROUP(1);
3755 case 17 ... 21:
3756 return 2;
3757 case 22 ... 24:
3758 return PHY_TSSI_EXTRA_GROUP(2);
3759 case 25 ... 29:
3760 return 3;
3761 case 33 ... 37:
3762 return 4;
3763 case 38 ... 40:
3764 return PHY_TSSI_EXTRA_GROUP(4);
3765 case 41 ... 45:
3766 return 5;
3767 case 46 ... 48:
3768 return PHY_TSSI_EXTRA_GROUP(5);
3769 case 49 ... 53:
3770 return 6;
3771 case 54 ... 56:
3772 return PHY_TSSI_EXTRA_GROUP(6);
3773 case 57 ... 61:
3774 return 7;
3775 case 65 ... 69:
3776 return 8;
3777 case 70 ... 72:
3778 return PHY_TSSI_EXTRA_GROUP(8);
3779 case 73 ... 77:
3780 return 9;
3781 case 78 ... 80:
3782 return PHY_TSSI_EXTRA_GROUP(9);
3783 case 81 ... 85:
3784 return 10;
3785 case 86 ... 88:
3786 return PHY_TSSI_EXTRA_GROUP(10);
3787 case 89 ... 93:
3788 return 11;
3789 case 97 ... 101:
3790 return 12;
3791 case 102 ... 104:
3792 return PHY_TSSI_EXTRA_GROUP(12);
3793 case 105 ... 109:
3794 return 13;
3795 case 110 ... 112:
3796 return PHY_TSSI_EXTRA_GROUP(13);
3797 case 113 ... 117:
3798 return 14;
3799 case 118 ... 120:
3800 return PHY_TSSI_EXTRA_GROUP(14);
3801 case 121 ... 125:
3802 return 15;
3803 case 129 ... 133:
3804 return 16;
3805 case 134 ... 136:
3806 return PHY_TSSI_EXTRA_GROUP(16);
3807 case 137 ... 141:
3808 return 17;
3809 case 142 ... 144:
3810 return PHY_TSSI_EXTRA_GROUP(17);
3811 case 145 ... 149:
3812 return 18;
3813 case 150 ... 152:
3814 return PHY_TSSI_EXTRA_GROUP(18);
3815 case 153 ... 157:
3816 return 19;
3817 case 161 ... 165:
3818 return 20;
3819 case 166 ... 168:
3820 return PHY_TSSI_EXTRA_GROUP(20);
3821 case 169 ... 173:
3822 return 21;
3823 case 174 ... 176:
3824 return PHY_TSSI_EXTRA_GROUP(21);
3825 case 177 ... 181:
3826 return 22;
3827 case 182 ... 184:
3828 return PHY_TSSI_EXTRA_GROUP(22);
3829 case 185 ... 189:
3830 return 23;
3831 case 193 ... 197:
3832 return 24;
3833 case 198 ... 200:
3834 return PHY_TSSI_EXTRA_GROUP(24);
3835 case 201 ... 205:
3836 return 25;
3837 case 206 ... 208:
3838 return PHY_TSSI_EXTRA_GROUP(25);
3839 case 209 ... 213:
3840 return 26;
3841 case 214 ... 216:
3842 return PHY_TSSI_EXTRA_GROUP(26);
3843 case 217 ... 221:
3844 return 27;
3845 case 225 ... 229:
3846 return 28;
3847 case 230 ... 232:
3848 return PHY_TSSI_EXTRA_GROUP(28);
3849 case 233 ... 237:
3850 return 29;
3851 case 238 ... 240:
3852 return PHY_TSSI_EXTRA_GROUP(29);
3853 case 241 ... 245:
3854 return 30;
3855 case 246 ... 248:
3856 return PHY_TSSI_EXTRA_GROUP(30);
3857 case 249 ... 253:
3858 return 31;
3859 }
3860
3861 return 0;
3862 }
3863
phy_tssi_get_trim_group(u8 ch)3864 static u32 phy_tssi_get_trim_group(u8 ch)
3865 {
3866 switch (ch) {
3867 case 1 ... 8:
3868 return 0;
3869 case 9 ... 14:
3870 return 1;
3871 case 36 ... 48:
3872 return 2;
3873 case 49 ... 51:
3874 return PHY_TSSI_EXTRA_GROUP(2);
3875 case 52 ... 64:
3876 return 3;
3877 case 100 ... 112:
3878 return 4;
3879 case 113 ... 115:
3880 return PHY_TSSI_EXTRA_GROUP(4);
3881 case 116 ... 128:
3882 return 5;
3883 case 132 ... 144:
3884 return 6;
3885 case 149 ... 177:
3886 return 7;
3887 }
3888
3889 return 0;
3890 }
3891
phy_tssi_get_6g_trim_group(u8 ch)3892 static u32 phy_tssi_get_6g_trim_group(u8 ch)
3893 {
3894 switch (ch) {
3895 case 1 ... 13:
3896 return 0;
3897 case 14 ... 16:
3898 return PHY_TSSI_EXTRA_GROUP(0);
3899 case 17 ... 29:
3900 return 1;
3901 case 33 ... 45:
3902 return 2;
3903 case 46 ... 48:
3904 return PHY_TSSI_EXTRA_GROUP(2);
3905 case 49 ... 61:
3906 return 3;
3907 case 65 ... 77:
3908 return 4;
3909 case 78 ... 80:
3910 return PHY_TSSI_EXTRA_GROUP(4);
3911 case 81 ... 93:
3912 return 5;
3913 case 97 ... 109:
3914 return 6;
3915 case 110 ... 112:
3916 return PHY_TSSI_EXTRA_GROUP(6);
3917 case 113 ... 125:
3918 return 7;
3919 case 129 ... 141:
3920 return 8;
3921 case 142 ... 144:
3922 return PHY_TSSI_EXTRA_GROUP(8);
3923 case 145 ... 157:
3924 return 9;
3925 case 161 ... 173:
3926 return 10;
3927 case 174 ... 176:
3928 return PHY_TSSI_EXTRA_GROUP(10);
3929 case 177 ... 189:
3930 return 11;
3931 case 193 ... 205:
3932 return 12;
3933 case 206 ... 208:
3934 return PHY_TSSI_EXTRA_GROUP(12);
3935 case 209 ... 221:
3936 return 13;
3937 case 225 ... 237:
3938 return 14;
3939 case 238 ... 240:
3940 return PHY_TSSI_EXTRA_GROUP(14);
3941 case 241 ... 253:
3942 return 15;
3943 }
3944
3945 return 0;
3946 }
3947
phy_tssi_get_ofdm_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)3948 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev,
3949 enum rtw89_phy_idx phy,
3950 const struct rtw89_chan *chan,
3951 enum rtw89_rf_path path)
3952 {
3953 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
3954 enum rtw89_band band = chan->band_type;
3955 u8 ch = chan->channel;
3956 u32 gidx_1st;
3957 u32 gidx_2nd;
3958 s8 de_1st;
3959 s8 de_2nd;
3960 u32 gidx;
3961 s8 val;
3962
3963 if (band == RTW89_BAND_6G)
3964 goto calc_6g;
3965
3966 gidx = phy_tssi_get_ofdm_group(ch);
3967
3968 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3969 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3970 path, gidx);
3971
3972 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
3973 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
3974 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
3975 de_1st = tssi_info->tssi_mcs[path][gidx_1st];
3976 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd];
3977 val = (de_1st + de_2nd) / 2;
3978
3979 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3980 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
3981 path, val, de_1st, de_2nd);
3982 } else {
3983 val = tssi_info->tssi_mcs[path][gidx];
3984
3985 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3986 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
3987 }
3988
3989 return val;
3990
3991 calc_6g:
3992 gidx = phy_tssi_get_6g_ofdm_group(ch);
3993
3994 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
3995 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n",
3996 path, gidx);
3997
3998 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) {
3999 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx);
4000 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx);
4001 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st];
4002 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd];
4003 val = (de_1st + de_2nd) / 2;
4004
4005 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4006 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n",
4007 path, val, de_1st, de_2nd);
4008 } else {
4009 val = tssi_info->tssi_6g_mcs[path][gidx];
4010
4011 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4012 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val);
4013 }
4014
4015 return val;
4016 }
4017
phy_tssi_get_ofdm_trim_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,enum rtw89_rf_path path)4018 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev,
4019 enum rtw89_phy_idx phy,
4020 const struct rtw89_chan *chan,
4021 enum rtw89_rf_path path)
4022 {
4023 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4024 enum rtw89_band band = chan->band_type;
4025 u8 ch = chan->channel;
4026 u32 tgidx_1st;
4027 u32 tgidx_2nd;
4028 s8 tde_1st;
4029 s8 tde_2nd;
4030 u32 tgidx;
4031 s8 val;
4032
4033 if (band == RTW89_BAND_6G)
4034 goto calc_6g;
4035
4036 tgidx = phy_tssi_get_trim_group(ch);
4037
4038 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4039 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4040 path, tgidx);
4041
4042 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4043 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4044 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4045 tde_1st = tssi_info->tssi_trim[path][tgidx_1st];
4046 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd];
4047 val = (tde_1st + tde_2nd) / 2;
4048
4049 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4050 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4051 path, val, tde_1st, tde_2nd);
4052 } else {
4053 val = tssi_info->tssi_trim[path][tgidx];
4054
4055 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4056 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4057 path, val);
4058 }
4059
4060 return val;
4061
4062 calc_6g:
4063 tgidx = phy_tssi_get_6g_trim_group(ch);
4064
4065 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4066 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n",
4067 path, tgidx);
4068
4069 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) {
4070 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx);
4071 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx);
4072 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st];
4073 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd];
4074 val = (tde_1st + tde_2nd) / 2;
4075
4076 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4077 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n",
4078 path, val, tde_1st, tde_2nd);
4079 } else {
4080 val = tssi_info->tssi_trim_6g[path][tgidx];
4081
4082 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4083 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n",
4084 path, val);
4085 }
4086
4087 return val;
4088 }
4089
rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4090 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
4091 enum rtw89_phy_idx phy,
4092 const struct rtw89_chan *chan,
4093 struct rtw89_h2c_rf_tssi *h2c)
4094 {
4095 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4096 u8 ch = chan->channel;
4097 s8 trim_de;
4098 s8 ofdm_de;
4099 s8 cck_de;
4100 u8 gidx;
4101 s8 val;
4102 int i;
4103
4104 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n",
4105 phy, ch);
4106
4107 for (i = RF_PATH_A; i <= RF_PATH_B; i++) {
4108 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i);
4109 h2c->curr_tssi_trim_de[i] = trim_de;
4110
4111 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4112 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de);
4113
4114 gidx = phy_tssi_get_cck_group(ch);
4115 cck_de = tssi_info->tssi_cck[i][gidx];
4116 val = u32_get_bits(cck_de + trim_de, 0xff);
4117
4118 h2c->curr_tssi_cck_de[i] = 0x0;
4119 h2c->curr_tssi_cck_de_20m[i] = val;
4120 h2c->curr_tssi_cck_de_40m[i] = val;
4121 h2c->curr_tssi_efuse_cck_de[i] = cck_de;
4122
4123 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4124 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de);
4125
4126 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i);
4127 val = u32_get_bits(ofdm_de + trim_de, 0xff);
4128
4129 h2c->curr_tssi_ofdm_de[i] = 0x0;
4130 h2c->curr_tssi_ofdm_de_20m[i] = val;
4131 h2c->curr_tssi_ofdm_de_40m[i] = val;
4132 h2c->curr_tssi_ofdm_de_80m[i] = val;
4133 h2c->curr_tssi_ofdm_de_160m[i] = val;
4134 h2c->curr_tssi_ofdm_de_320m[i] = val;
4135 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de;
4136
4137 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4138 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de);
4139 }
4140 }
4141
rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy,const struct rtw89_chan * chan,struct rtw89_h2c_rf_tssi * h2c)4142 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
4143 enum rtw89_phy_idx phy,
4144 const struct rtw89_chan *chan,
4145 struct rtw89_h2c_rf_tssi *h2c)
4146 {
4147 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk;
4148 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi;
4149 const s8 *thm_up[RF_PATH_B + 1] = {};
4150 const s8 *thm_down[RF_PATH_B + 1] = {};
4151 u8 subband = chan->subband_type;
4152 s8 thm_ofst[128] = {0};
4153 u8 thermal;
4154 u8 path;
4155 u8 i, j;
4156
4157 switch (subband) {
4158 default:
4159 case RTW89_CH_2G:
4160 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0];
4161 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0];
4162 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0];
4163 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0];
4164 break;
4165 case RTW89_CH_5G_BAND_1:
4166 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0];
4167 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0];
4168 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0];
4169 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0];
4170 break;
4171 case RTW89_CH_5G_BAND_3:
4172 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1];
4173 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1];
4174 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1];
4175 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1];
4176 break;
4177 case RTW89_CH_5G_BAND_4:
4178 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2];
4179 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2];
4180 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2];
4181 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2];
4182 break;
4183 case RTW89_CH_6G_BAND_IDX0:
4184 case RTW89_CH_6G_BAND_IDX1:
4185 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0];
4186 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0];
4187 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0];
4188 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0];
4189 break;
4190 case RTW89_CH_6G_BAND_IDX2:
4191 case RTW89_CH_6G_BAND_IDX3:
4192 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1];
4193 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1];
4194 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1];
4195 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1];
4196 break;
4197 case RTW89_CH_6G_BAND_IDX4:
4198 case RTW89_CH_6G_BAND_IDX5:
4199 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2];
4200 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2];
4201 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2];
4202 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2];
4203 break;
4204 case RTW89_CH_6G_BAND_IDX6:
4205 case RTW89_CH_6G_BAND_IDX7:
4206 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3];
4207 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3];
4208 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3];
4209 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3];
4210 break;
4211 }
4212
4213 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4214 "[TSSI] tmeter tbl on subband: %u\n", subband);
4215
4216 for (path = RF_PATH_A; path <= RF_PATH_B; path++) {
4217 thermal = tssi_info->thermal[path];
4218 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4219 "path: %u, pg thermal: 0x%x\n", path, thermal);
4220
4221 if (thermal == 0xff) {
4222 h2c->pg_thermal[path] = 0x38;
4223 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path]));
4224 continue;
4225 }
4226
4227 h2c->pg_thermal[path] = thermal;
4228
4229 i = 0;
4230 for (j = 0; j < 64; j++)
4231 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4232 thm_up[path][i++] :
4233 thm_up[path][DELTA_SWINGIDX_SIZE - 1];
4234
4235 i = 1;
4236 for (j = 127; j >= 64; j--)
4237 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ?
4238 -thm_down[path][i++] :
4239 -thm_down[path][DELTA_SWINGIDX_SIZE - 1];
4240
4241 for (i = 0; i < 128; i += 4) {
4242 h2c->ftable[path][i + 0] = thm_ofst[i + 3];
4243 h2c->ftable[path][i + 1] = thm_ofst[i + 2];
4244 h2c->ftable[path][i + 2] = thm_ofst[i + 1];
4245 h2c->ftable[path][i + 3] = thm_ofst[i + 0];
4246
4247 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
4248 "thm ofst [%x]: %02x %02x %02x %02x\n",
4249 i, thm_ofst[i], thm_ofst[i + 1],
4250 thm_ofst[i + 2], thm_ofst[i + 3]);
4251 }
4252 }
4253 }
4254
rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo)4255 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo)
4256 {
4257 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4258 u32 reg_mask;
4259
4260 if (sc_xo)
4261 reg_mask = xtal->sc_xo_mask;
4262 else
4263 reg_mask = xtal->sc_xi_mask;
4264
4265 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask);
4266 }
4267
rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev * rtwdev,bool sc_xo,u8 val)4268 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo,
4269 u8 val)
4270 {
4271 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info;
4272 u32 reg_mask;
4273
4274 if (sc_xo)
4275 reg_mask = xtal->sc_xo_mask;
4276 else
4277 reg_mask = xtal->sc_xi_mask;
4278
4279 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val);
4280 }
4281
rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev * rtwdev,u8 crystal_cap,bool force)4282 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev,
4283 u8 crystal_cap, bool force)
4284 {
4285 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4286 const struct rtw89_chip_info *chip = rtwdev->chip;
4287 u8 sc_xi_val, sc_xo_val;
4288
4289 if (!force && cfo->crystal_cap == crystal_cap)
4290 return;
4291 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) {
4292 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap);
4293 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap);
4294 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true);
4295 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false);
4296 } else {
4297 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO,
4298 crystal_cap, XTAL_SC_XO_MASK);
4299 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI,
4300 crystal_cap, XTAL_SC_XI_MASK);
4301 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val);
4302 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val);
4303 }
4304 cfo->crystal_cap = sc_xi_val;
4305 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap);
4306
4307 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val);
4308 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val);
4309 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n",
4310 cfo->x_cap_ofst);
4311 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n");
4312 }
4313
rtw89_phy_cfo_reset(struct rtw89_dev * rtwdev)4314 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev)
4315 {
4316 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4317 u8 cap;
4318
4319 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK;
4320 cfo->is_adjust = false;
4321 if (cfo->crystal_cap == cfo->def_x_cap)
4322 return;
4323 cap = cfo->crystal_cap;
4324 cap += (cap > cfo->def_x_cap ? -1 : 1);
4325 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false);
4326 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4327 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap,
4328 cfo->def_x_cap);
4329 }
4330
rtw89_dcfo_comp(struct rtw89_dev * rtwdev,s32 curr_cfo)4331 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo)
4332 {
4333 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp;
4334 bool is_linked = rtwdev->total_sta_assoc > 0;
4335 s32 cfo_avg_312;
4336 s32 dcfo_comp_val;
4337 int sign;
4338
4339 if (rtwdev->chip->chip_id == RTL8922A)
4340 return;
4341
4342 if (!is_linked) {
4343 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n",
4344 is_linked);
4345 return;
4346 }
4347 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo);
4348 if (curr_cfo == 0)
4349 return;
4350 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO);
4351 sign = curr_cfo > 0 ? 1 : -1;
4352 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val;
4353 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312);
4354 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV)
4355 cfo_avg_312 = -cfo_avg_312;
4356 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask,
4357 cfo_avg_312);
4358 }
4359
rtw89_dcfo_comp_init(struct rtw89_dev * rtwdev)4360 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev)
4361 {
4362 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
4363 const struct rtw89_chip_info *chip = rtwdev->chip;
4364 const struct rtw89_cfo_regs *cfo = phy->cfo;
4365
4366 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1);
4367 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8);
4368
4369 if (chip->chip_gen == RTW89_CHIP_AX) {
4370 if (chip->cfo_hw_comp) {
4371 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2,
4372 B_AX_PWR_UL_CFO_MASK, 0x6);
4373 } else {
4374 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1);
4375 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2,
4376 B_AX_PWR_UL_CFO_MASK);
4377 }
4378 }
4379 }
4380
rtw89_phy_cfo_init(struct rtw89_dev * rtwdev)4381 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev)
4382 {
4383 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4384 struct rtw89_efuse *efuse = &rtwdev->efuse;
4385
4386 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK;
4387 cfo->crystal_cap = cfo->crystal_cap_default;
4388 cfo->def_x_cap = cfo->crystal_cap;
4389 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f);
4390 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1);
4391 cfo->is_adjust = false;
4392 cfo->divergence_lock_en = false;
4393 cfo->x_cap_ofst = 0;
4394 cfo->lock_cnt = 0;
4395 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE;
4396 cfo->apply_compensation = false;
4397 cfo->residual_cfo_acc = 0;
4398 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n",
4399 cfo->crystal_cap_default);
4400 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true);
4401 rtw89_dcfo_comp_init(rtwdev);
4402 cfo->cfo_timer_ms = 2000;
4403 cfo->cfo_trig_by_timer_en = false;
4404 cfo->phy_cfo_trk_cnt = 0;
4405 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4406 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE;
4407 }
4408
rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev * rtwdev,s32 curr_cfo)4409 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev,
4410 s32 curr_cfo)
4411 {
4412 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4413 int crystal_cap = cfo->crystal_cap;
4414 s32 cfo_abs = abs(curr_cfo);
4415 int sign;
4416
4417 if (curr_cfo == 0) {
4418 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n");
4419 return;
4420 }
4421 if (!cfo->is_adjust) {
4422 if (cfo_abs > CFO_TRK_ENABLE_TH)
4423 cfo->is_adjust = true;
4424 } else {
4425 if (cfo_abs <= CFO_TRK_STOP_TH)
4426 cfo->is_adjust = false;
4427 }
4428 if (!cfo->is_adjust) {
4429 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n");
4430 return;
4431 }
4432 sign = curr_cfo > 0 ? 1 : -1;
4433 if (cfo_abs > CFO_TRK_STOP_TH_4)
4434 crystal_cap += 3 * sign;
4435 else if (cfo_abs > CFO_TRK_STOP_TH_3)
4436 crystal_cap += 3 * sign;
4437 else if (cfo_abs > CFO_TRK_STOP_TH_2)
4438 crystal_cap += 1 * sign;
4439 else if (cfo_abs > CFO_TRK_STOP_TH_1)
4440 crystal_cap += 1 * sign;
4441 else
4442 return;
4443
4444 crystal_cap = clamp(crystal_cap, 0, 127);
4445 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false);
4446 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4447 "X_cap{Curr,Default}={0x%x,0x%x}\n",
4448 cfo->crystal_cap, cfo->def_x_cap);
4449 }
4450
rtw89_phy_average_cfo_calc(struct rtw89_dev * rtwdev)4451 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev)
4452 {
4453 const struct rtw89_chip_info *chip = rtwdev->chip;
4454 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4455 s32 cfo_khz_all = 0;
4456 s32 cfo_cnt_all = 0;
4457 s32 cfo_all_avg = 0;
4458 u8 i;
4459
4460 if (rtwdev->total_sta_assoc != 1)
4461 return 0;
4462 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n");
4463 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4464 if (cfo->cfo_cnt[i] == 0)
4465 continue;
4466 cfo_khz_all += cfo->cfo_tail[i];
4467 cfo_cnt_all += cfo->cfo_cnt[i];
4468 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all);
4469 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4470 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft,
4471 cfo_cnt_all);
4472 }
4473 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4474 "CFO track for macid = %d\n", i);
4475 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4476 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n",
4477 cfo_khz_all, cfo_cnt_all, cfo_all_avg);
4478 return cfo_all_avg;
4479 }
4480
rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev * rtwdev)4481 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev)
4482 {
4483 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4484 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4485 s32 target_cfo = 0;
4486 s32 cfo_khz_all = 0;
4487 s32 cfo_khz_all_tp_wgt = 0;
4488 s32 cfo_avg = 0;
4489 s32 max_cfo_lb = BIT(31);
4490 s32 min_cfo_ub = GENMASK(30, 0);
4491 u16 cfo_cnt_all = 0;
4492 u8 active_entry_cnt = 0;
4493 u8 sta_cnt = 0;
4494 u32 tp_all = 0;
4495 u8 i;
4496 u8 cfo_tol = 0;
4497
4498 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n");
4499 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) {
4500 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n");
4501 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4502 if (cfo->cfo_cnt[i] == 0)
4503 continue;
4504 cfo_khz_all += cfo->cfo_tail[i];
4505 cfo_cnt_all += cfo->cfo_cnt[i];
4506 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all);
4507 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4508 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n",
4509 cfo_khz_all, cfo_cnt_all, cfo_avg);
4510 target_cfo = cfo_avg;
4511 }
4512 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) {
4513 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n");
4514 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4515 if (cfo->cfo_cnt[i] == 0)
4516 continue;
4517 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4518 (s32)cfo->cfo_cnt[i]);
4519 cfo_khz_all += cfo->cfo_avg[i];
4520 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4521 "Macid=%d, cfo_avg=%d\n", i,
4522 cfo->cfo_avg[i]);
4523 }
4524 sta_cnt = rtwdev->total_sta_assoc;
4525 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt);
4526 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4527 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n",
4528 cfo_khz_all, sta_cnt, cfo_avg);
4529 target_cfo = cfo_avg;
4530 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) {
4531 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n");
4532 cfo_tol = cfo->sta_cfo_tolerance;
4533 for (i = 0; i < CFO_TRACK_MAX_USER; i++) {
4534 sta_cnt++;
4535 if (cfo->cfo_cnt[i] != 0) {
4536 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i],
4537 (s32)cfo->cfo_cnt[i]);
4538 active_entry_cnt++;
4539 } else {
4540 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i];
4541 }
4542 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb);
4543 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub);
4544 cfo_khz_all += cfo->cfo_avg[i];
4545 /* need tp for each entry */
4546 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4547 "[%d] cfo_avg=%d, tp=tbd\n",
4548 i, cfo->cfo_avg[i]);
4549 if (sta_cnt >= rtwdev->total_sta_assoc)
4550 break;
4551 }
4552 tp_all = stats->rx_throughput; /* need tp for each entry */
4553 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all);
4554
4555 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n",
4556 sta_cnt);
4557 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n",
4558 active_entry_cnt);
4559 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4560 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n",
4561 cfo_khz_all_tp_wgt, cfo_avg);
4562 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n",
4563 max_cfo_lb, min_cfo_ub);
4564 if (max_cfo_lb <= min_cfo_ub) {
4565 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4566 "cfo win_size=%d\n",
4567 min_cfo_ub - max_cfo_lb);
4568 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub);
4569 } else {
4570 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4571 "No intersection of cfo tolerance windows\n");
4572 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt);
4573 }
4574 for (i = 0; i < CFO_TRACK_MAX_USER; i++)
4575 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i];
4576 }
4577 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo);
4578 return target_cfo;
4579 }
4580
rtw89_phy_cfo_statistics_reset(struct rtw89_dev * rtwdev)4581 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev)
4582 {
4583 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4584
4585 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail));
4586 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt));
4587 cfo->packet_count = 0;
4588 cfo->packet_count_pre = 0;
4589 cfo->cfo_avg_pre = 0;
4590 }
4591
rtw89_phy_cfo_dm(struct rtw89_dev * rtwdev)4592 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev)
4593 {
4594 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4595 s32 new_cfo = 0;
4596 bool x_cap_update = false;
4597 u8 pre_x_cap = cfo->crystal_cap;
4598 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft;
4599
4600 cfo->dcfo_avg = 0;
4601 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n",
4602 rtwdev->total_sta_assoc);
4603 if (rtwdev->total_sta_assoc == 0) {
4604 rtw89_phy_cfo_reset(rtwdev);
4605 return;
4606 }
4607 if (cfo->packet_count == 0) {
4608 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n");
4609 return;
4610 }
4611 if (cfo->packet_count == cfo->packet_count_pre) {
4612 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n");
4613 return;
4614 }
4615 if (rtwdev->total_sta_assoc == 1)
4616 new_cfo = rtw89_phy_average_cfo_calc(rtwdev);
4617 else
4618 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev);
4619 if (cfo->divergence_lock_en) {
4620 cfo->lock_cnt++;
4621 if (cfo->lock_cnt > CFO_PERIOD_CNT) {
4622 cfo->divergence_lock_en = false;
4623 cfo->lock_cnt = 0;
4624 } else {
4625 rtw89_phy_cfo_reset(rtwdev);
4626 }
4627 return;
4628 }
4629 if (cfo->crystal_cap >= cfo->x_cap_ub ||
4630 cfo->crystal_cap <= cfo->x_cap_lb) {
4631 cfo->divergence_lock_en = true;
4632 rtw89_phy_cfo_reset(rtwdev);
4633 return;
4634 }
4635
4636 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo);
4637 cfo->cfo_avg_pre = new_cfo;
4638 cfo->dcfo_avg_pre = cfo->dcfo_avg;
4639 x_cap_update = cfo->crystal_cap != pre_x_cap;
4640 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update);
4641 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n",
4642 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap,
4643 cfo->x_cap_ofst);
4644 if (x_cap_update) {
4645 if (cfo->dcfo_avg > 0)
4646 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4647 else
4648 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft;
4649 }
4650 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg);
4651 rtw89_phy_cfo_statistics_reset(rtwdev);
4652 }
4653
rtw89_phy_cfo_track_work(struct work_struct * work)4654 void rtw89_phy_cfo_track_work(struct work_struct *work)
4655 {
4656 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4657 cfo_track_work.work);
4658 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4659
4660 mutex_lock(&rtwdev->mutex);
4661 if (!cfo->cfo_trig_by_timer_en)
4662 goto out;
4663 rtw89_leave_ps_mode(rtwdev);
4664 rtw89_phy_cfo_dm(rtwdev);
4665 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4666 msecs_to_jiffies(cfo->cfo_timer_ms));
4667 out:
4668 mutex_unlock(&rtwdev->mutex);
4669 }
4670
rtw89_phy_cfo_start_work(struct rtw89_dev * rtwdev)4671 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev)
4672 {
4673 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4674
4675 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work,
4676 msecs_to_jiffies(cfo->cfo_timer_ms));
4677 }
4678
rtw89_phy_cfo_track(struct rtw89_dev * rtwdev)4679 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev)
4680 {
4681 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4682 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4683 bool is_ul_ofdma = false, ofdma_acc_en = false;
4684
4685 if (stats->rx_tf_periodic > CFO_TF_CNT_TH)
4686 is_ul_ofdma = true;
4687 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE &&
4688 is_ul_ofdma)
4689 ofdma_acc_en = true;
4690
4691 switch (cfo->phy_cfo_status) {
4692 case RTW89_PHY_DCFO_STATE_NORMAL:
4693 if (stats->tx_throughput >= CFO_TP_UPPER) {
4694 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE;
4695 cfo->cfo_trig_by_timer_en = true;
4696 cfo->cfo_timer_ms = CFO_COMP_PERIOD;
4697 rtw89_phy_cfo_start_work(rtwdev);
4698 }
4699 break;
4700 case RTW89_PHY_DCFO_STATE_ENHANCE:
4701 if (stats->tx_throughput <= CFO_TP_LOWER)
4702 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4703 else if (ofdma_acc_en &&
4704 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT)
4705 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD;
4706 else
4707 cfo->phy_cfo_trk_cnt++;
4708
4709 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) {
4710 cfo->phy_cfo_trk_cnt = 0;
4711 cfo->cfo_trig_by_timer_en = false;
4712 }
4713 break;
4714 case RTW89_PHY_DCFO_STATE_HOLD:
4715 if (stats->tx_throughput <= CFO_TP_LOWER) {
4716 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4717 cfo->phy_cfo_trk_cnt = 0;
4718 cfo->cfo_trig_by_timer_en = false;
4719 } else {
4720 cfo->phy_cfo_trk_cnt++;
4721 }
4722 break;
4723 default:
4724 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL;
4725 cfo->phy_cfo_trk_cnt = 0;
4726 break;
4727 }
4728 rtw89_debug(rtwdev, RTW89_DBG_CFO,
4729 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n",
4730 stats->tx_throughput, cfo->phy_cfo_status,
4731 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt,
4732 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0]));
4733 if (cfo->cfo_trig_by_timer_en)
4734 return;
4735 rtw89_phy_cfo_dm(rtwdev);
4736 }
4737
rtw89_phy_cfo_parse(struct rtw89_dev * rtwdev,s16 cfo_val,struct rtw89_rx_phy_ppdu * phy_ppdu)4738 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
4739 struct rtw89_rx_phy_ppdu *phy_ppdu)
4740 {
4741 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking;
4742 u8 macid = phy_ppdu->mac_id;
4743
4744 if (macid >= CFO_TRACK_MAX_USER) {
4745 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid);
4746 return;
4747 }
4748
4749 cfo->cfo_tail[macid] += cfo_val;
4750 cfo->cfo_cnt[macid]++;
4751 cfo->packet_count++;
4752 }
4753
rtw89_phy_ul_tb_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4754 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link)
4755 {
4756 const struct rtw89_chip_info *chip = rtwdev->chip;
4757 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
4758 rtwvif_link->chanctx_idx);
4759 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4760
4761 if (!chip->ul_tb_waveform_ctrl)
4762 return;
4763
4764 rtwvif_link->def_tri_idx =
4765 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG);
4766
4767 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV)
4768 rtwvif_link->dyn_tb_bedge_en = false;
4769 else if (chan->band_type >= RTW89_BAND_5G &&
4770 chan->band_width >= RTW89_CHANNEL_WIDTH_40)
4771 rtwvif_link->dyn_tb_bedge_en = true;
4772 else
4773 rtwvif_link->dyn_tb_bedge_en = false;
4774
4775 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4776 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n",
4777 ul_tb_info->def_if_bandedge, rtwvif_link->def_tri_idx);
4778 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4779 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n",
4780 rtwvif_link->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en);
4781 }
4782
4783 struct rtw89_phy_ul_tb_check_data {
4784 bool valid;
4785 bool high_tf_client;
4786 bool low_tf_client;
4787 bool dyn_tb_bedge_en;
4788 u8 def_tri_idx;
4789 };
4790
4791 struct rtw89_phy_power_diff {
4792 u32 q_00;
4793 u32 q_11;
4794 u32 q_matrix_en;
4795 u32 ultb_1t_norm_160;
4796 u32 ultb_2t_norm_160;
4797 u32 com1_norm_1sts;
4798 u32 com2_resp_1sts_path;
4799 };
4800
rtw89_phy_ofdma_power_diff(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4801 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev,
4802 struct rtw89_vif_link *rtwvif_link)
4803 {
4804 static const struct rtw89_phy_power_diff table[2] = {
4805 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3},
4806 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1},
4807 };
4808 const struct rtw89_phy_power_diff *param;
4809 u32 reg;
4810
4811 if (!rtwdev->chip->ul_tb_pwr_diff)
4812 return;
4813
4814 if (rtwvif_link->pwr_diff_en == rtwvif_link->pre_pwr_diff_en) {
4815 rtwvif_link->pwr_diff_en = false;
4816 return;
4817 }
4818
4819 rtwvif_link->pre_pwr_diff_en = rtwvif_link->pwr_diff_en;
4820 param = &table[rtwvif_link->pwr_diff_en];
4821
4822 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL,
4823 param->q_00);
4824 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL,
4825 param->q_11);
4826 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX,
4827 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en);
4828
4829 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif_link->mac_idx);
4830 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160,
4831 param->ultb_1t_norm_160);
4832
4833 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif_link->mac_idx);
4834 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160,
4835 param->ultb_2t_norm_160);
4836
4837 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif_link->mac_idx);
4838 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS,
4839 param->com1_norm_1sts);
4840
4841 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif_link->mac_idx);
4842 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH,
4843 param->com2_resp_1sts_path);
4844 }
4845
4846 static
rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4847 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev,
4848 struct rtw89_vif_link *rtwvif_link,
4849 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4850 {
4851 struct rtw89_traffic_stats *stats = &rtwdev->stats;
4852 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4853
4854 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
4855 return;
4856
4857 if (!vif->cfg.assoc)
4858 return;
4859
4860 if (rtwdev->chip->ul_tb_waveform_ctrl) {
4861 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH)
4862 ul_tb_data->high_tf_client = true;
4863 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH)
4864 ul_tb_data->low_tf_client = true;
4865
4866 ul_tb_data->valid = true;
4867 ul_tb_data->def_tri_idx = rtwvif_link->def_tri_idx;
4868 ul_tb_data->dyn_tb_bedge_en = rtwvif_link->dyn_tb_bedge_en;
4869 }
4870
4871 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif_link);
4872 }
4873
rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev * rtwdev,struct rtw89_phy_ul_tb_check_data * ul_tb_data)4874 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev,
4875 struct rtw89_phy_ul_tb_check_data *ul_tb_data)
4876 {
4877 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4878
4879 if (!rtwdev->chip->ul_tb_waveform_ctrl)
4880 return;
4881
4882 if (ul_tb_data->dyn_tb_bedge_en) {
4883 if (ul_tb_data->high_tf_client) {
4884 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0);
4885 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4886 "[ULTB] Turn off if_bandedge\n");
4887 } else if (ul_tb_data->low_tf_client) {
4888 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN,
4889 ul_tb_info->def_if_bandedge);
4890 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4891 "[ULTB] Set to default if_bandedge = %d\n",
4892 ul_tb_info->def_if_bandedge);
4893 }
4894 }
4895
4896 if (ul_tb_info->dyn_tb_tri_en) {
4897 if (ul_tb_data->high_tf_client) {
4898 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4899 B_TXSHAPE_TRIANGULAR_CFG, 0);
4900 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4901 "[ULTB] Turn off Tx triangle\n");
4902 } else if (ul_tb_data->low_tf_client) {
4903 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT,
4904 B_TXSHAPE_TRIANGULAR_CFG,
4905 ul_tb_data->def_tri_idx);
4906 rtw89_debug(rtwdev, RTW89_DBG_UL_TB,
4907 "[ULTB] Set to default tx_shap_idx = %d\n",
4908 ul_tb_data->def_tri_idx);
4909 }
4910 }
4911 }
4912
rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev * rtwdev)4913 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev)
4914 {
4915 const struct rtw89_chip_info *chip = rtwdev->chip;
4916 struct rtw89_phy_ul_tb_check_data ul_tb_data = {};
4917 struct rtw89_vif_link *rtwvif_link;
4918 struct rtw89_vif *rtwvif;
4919 unsigned int link_id;
4920
4921 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff)
4922 return;
4923
4924 if (rtwdev->total_sta_assoc != 1)
4925 return;
4926
4927 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4928 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4929 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif_link, &ul_tb_data);
4930
4931 if (!ul_tb_data.valid)
4932 return;
4933
4934 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data);
4935 }
4936
rtw89_phy_ul_tb_info_init(struct rtw89_dev * rtwdev)4937 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev)
4938 {
4939 const struct rtw89_chip_info *chip = rtwdev->chip;
4940 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info;
4941
4942 if (!chip->ul_tb_waveform_ctrl)
4943 return;
4944
4945 ul_tb_info->dyn_tb_tri_en = true;
4946 ul_tb_info->def_if_bandedge =
4947 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN);
4948 }
4949
4950 static
rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats * antdiv_sts)4951 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts)
4952 {
4953 ewma_rssi_init(&antdiv_sts->cck_rssi_avg);
4954 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg);
4955 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg);
4956 antdiv_sts->pkt_cnt_cck = 0;
4957 antdiv_sts->pkt_cnt_ofdm = 0;
4958 antdiv_sts->pkt_cnt_non_legacy = 0;
4959 antdiv_sts->evm = 0;
4960 }
4961
rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_antdiv_stats * stats)4962 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev,
4963 struct rtw89_rx_phy_ppdu *phy_ppdu,
4964 struct rtw89_antdiv_stats *stats)
4965 {
4966 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) {
4967 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) {
4968 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg);
4969 stats->pkt_cnt_cck++;
4970 } else {
4971 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg);
4972 stats->pkt_cnt_ofdm++;
4973 stats->evm += phy_ppdu->ofdm.evm_min;
4974 }
4975 } else {
4976 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg);
4977 stats->pkt_cnt_non_legacy++;
4978 stats->evm += phy_ppdu->ofdm.evm_min;
4979 }
4980 }
4981
rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats * stats)4982 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats)
4983 {
4984 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck &&
4985 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm)
4986 return ewma_rssi_read(&stats->non_legacy_rssi_avg);
4987 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck &&
4988 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy)
4989 return ewma_rssi_read(&stats->ofdm_rssi_avg);
4990 else
4991 return ewma_rssi_read(&stats->cck_rssi_avg);
4992 }
4993
rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats * stats)4994 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats)
4995 {
4996 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm);
4997 }
4998
rtw89_phy_antdiv_parse(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)4999 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
5000 struct rtw89_rx_phy_ppdu *phy_ppdu)
5001 {
5002 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5003 struct rtw89_hal *hal = &rtwdev->hal;
5004
5005 if (!hal->ant_diversity || hal->ant_diversity_fixed)
5006 return;
5007
5008 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats);
5009
5010 if (!antdiv->get_stats)
5011 return;
5012
5013 if (hal->antenna_rx == RF_A)
5014 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats);
5015 else if (hal->antenna_rx == RF_B)
5016 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats);
5017 }
5018
rtw89_phy_antdiv_reg_init(struct rtw89_dev * rtwdev)5019 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev)
5020 {
5021 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN,
5022 0x0, RTW89_PHY_0);
5023 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL,
5024 0x0, RTW89_PHY_0);
5025
5026 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND,
5027 0x0, RTW89_PHY_0);
5028 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT,
5029 0x0, RTW89_PHY_0);
5030
5031 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN,
5032 0x0, RTW89_PHY_0);
5033
5034 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING,
5035 0x0100, RTW89_PHY_0);
5036
5037 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX,
5038 0x1, RTW89_PHY_0);
5039 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL,
5040 0x0, RTW89_PHY_0);
5041 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G,
5042 0x0, RTW89_PHY_0);
5043 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G,
5044 0x0, RTW89_PHY_0);
5045 }
5046
rtw89_phy_antdiv_sts_reset(struct rtw89_dev * rtwdev)5047 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev)
5048 {
5049 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5050
5051 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
5052 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats);
5053 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats);
5054 }
5055
rtw89_phy_antdiv_init(struct rtw89_dev * rtwdev)5056 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev)
5057 {
5058 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
5059 struct rtw89_hal *hal = &rtwdev->hal;
5060
5061 if (!hal->ant_diversity)
5062 return;
5063
5064 antdiv->get_stats = false;
5065 antdiv->rssi_pre = 0;
5066 rtw89_phy_antdiv_sts_reset(rtwdev);
5067 rtw89_phy_antdiv_reg_init(rtwdev);
5068 }
5069
rtw89_phy_thermal_protect(struct rtw89_dev * rtwdev)5070 static void rtw89_phy_thermal_protect(struct rtw89_dev *rtwdev)
5071 {
5072 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5073 struct rtw89_hal *hal = &rtwdev->hal;
5074 u8 th_max = phystat->last_thermal_max;
5075 u8 lv = hal->thermal_prot_lv;
5076
5077 if (!hal->thermal_prot_th ||
5078 (hal->disabled_dm_bitmap & BIT(RTW89_DM_THERMAL_PROTECT)))
5079 return;
5080
5081 if (th_max > hal->thermal_prot_th && lv < RTW89_THERMAL_PROT_LV_MAX)
5082 lv++;
5083 else if (th_max < hal->thermal_prot_th - 2 && lv > 0)
5084 lv--;
5085 else
5086 return;
5087
5088 hal->thermal_prot_lv = lv;
5089
5090 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, "thermal protection lv=%d\n", lv);
5091
5092 rtw89_fw_h2c_tx_duty(rtwdev, hal->thermal_prot_lv);
5093 }
5094
rtw89_phy_stat_thermal_update(struct rtw89_dev * rtwdev)5095 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev)
5096 {
5097 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5098 u8 th, th_max = 0;
5099 int i;
5100
5101 for (i = 0; i < rtwdev->chip->rf_path_num; i++) {
5102 th = rtw89_chip_get_thermal(rtwdev, i);
5103 if (th)
5104 ewma_thermal_add(&phystat->avg_thermal[i], th);
5105
5106 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK,
5107 "path(%d) thermal cur=%u avg=%ld", i, th,
5108 ewma_thermal_read(&phystat->avg_thermal[i]));
5109
5110 th_max = max(th_max, th);
5111 }
5112
5113 phystat->last_thermal_max = th_max;
5114 }
5115
5116 struct rtw89_phy_iter_rssi_data {
5117 struct rtw89_dev *rtwdev;
5118 struct rtw89_phy_ch_info *ch_info;
5119 bool rssi_changed;
5120 };
5121
5122 static
__rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link * rtwsta_link,struct rtw89_phy_iter_rssi_data * rssi_data)5123 void __rtw89_phy_stat_rssi_update_iter(struct rtw89_sta_link *rtwsta_link,
5124 struct rtw89_phy_iter_rssi_data *rssi_data)
5125 {
5126 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info;
5127 unsigned long rssi_curr;
5128
5129 rssi_curr = ewma_rssi_read(&rtwsta_link->avg_rssi);
5130
5131 if (rssi_curr < ch_info->rssi_min) {
5132 ch_info->rssi_min = rssi_curr;
5133 ch_info->rssi_min_macid = rtwsta_link->mac_id;
5134 }
5135
5136 if (rtwsta_link->prev_rssi == 0) {
5137 rtwsta_link->prev_rssi = rssi_curr;
5138 } else if (abs((int)rtwsta_link->prev_rssi - (int)rssi_curr) >
5139 (3 << RSSI_FACTOR)) {
5140 rtwsta_link->prev_rssi = rssi_curr;
5141 rssi_data->rssi_changed = true;
5142 }
5143 }
5144
rtw89_phy_stat_rssi_update_iter(void * data,struct ieee80211_sta * sta)5145 static void rtw89_phy_stat_rssi_update_iter(void *data,
5146 struct ieee80211_sta *sta)
5147 {
5148 struct rtw89_phy_iter_rssi_data *rssi_data =
5149 (struct rtw89_phy_iter_rssi_data *)data;
5150 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
5151 struct rtw89_sta_link *rtwsta_link;
5152 unsigned int link_id;
5153
5154 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id)
5155 __rtw89_phy_stat_rssi_update_iter(rtwsta_link, rssi_data);
5156 }
5157
rtw89_phy_stat_rssi_update(struct rtw89_dev * rtwdev)5158 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev)
5159 {
5160 struct rtw89_phy_iter_rssi_data rssi_data = {0};
5161
5162 rssi_data.rtwdev = rtwdev;
5163 rssi_data.ch_info = &rtwdev->ch_info;
5164 rssi_data.ch_info->rssi_min = U8_MAX;
5165 ieee80211_iterate_stations_atomic(rtwdev->hw,
5166 rtw89_phy_stat_rssi_update_iter,
5167 &rssi_data);
5168 if (rssi_data.rssi_changed)
5169 rtw89_btc_ntfy_wl_sta(rtwdev);
5170 }
5171
rtw89_phy_stat_init(struct rtw89_dev * rtwdev)5172 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev)
5173 {
5174 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5175 int i;
5176
5177 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
5178 ewma_thermal_init(&phystat->avg_thermal[i]);
5179
5180 rtw89_phy_stat_thermal_update(rtwdev);
5181
5182 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5183 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat));
5184
5185 ewma_rssi_init(&phystat->bcn_rssi);
5186
5187 rtwdev->hal.thermal_prot_lv = 0;
5188 }
5189
rtw89_phy_stat_track(struct rtw89_dev * rtwdev)5190 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev)
5191 {
5192 struct rtw89_phy_stat *phystat = &rtwdev->phystat;
5193
5194 rtw89_phy_stat_thermal_update(rtwdev);
5195 rtw89_phy_thermal_protect(rtwdev);
5196 rtw89_phy_stat_rssi_update(rtwdev);
5197
5198 phystat->last_pkt_stat = phystat->cur_pkt_stat;
5199 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat));
5200 }
5201
rtw89_phy_ccx_us_to_idx(struct rtw89_dev * rtwdev,u32 time_us)5202 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us)
5203 {
5204 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5205
5206 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5207 }
5208
rtw89_phy_ccx_idx_to_us(struct rtw89_dev * rtwdev,u16 idx)5209 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx)
5210 {
5211 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5212
5213 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx);
5214 }
5215
rtw89_phy_ccx_top_setting_init(struct rtw89_dev * rtwdev)5216 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev)
5217 {
5218 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5219 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5220 const struct rtw89_ccx_regs *ccx = phy->ccx;
5221
5222 env->ccx_manual_ctrl = false;
5223 env->ccx_ongoing = false;
5224 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5225 env->ccx_period = 0;
5226 env->ccx_unit_idx = RTW89_CCX_32_US;
5227
5228 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1);
5229 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1);
5230 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
5231 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask,
5232 RTW89_CCX_EDCCA_BW20_0);
5233 }
5234
rtw89_phy_ccx_get_report(struct rtw89_dev * rtwdev,u16 report,u16 score)5235 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report,
5236 u16 score)
5237 {
5238 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5239 u32 numer = 0;
5240 u16 ret = 0;
5241
5242 numer = report * score + (env->ccx_period >> 1);
5243 if (env->ccx_period)
5244 ret = numer / env->ccx_period;
5245
5246 return ret >= score ? score - 1 : ret;
5247 }
5248
rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev * rtwdev,u16 time_ms,u32 * period,u32 * unit_idx)5249 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev,
5250 u16 time_ms, u32 *period,
5251 u32 *unit_idx)
5252 {
5253 u32 idx;
5254 u8 quotient;
5255
5256 if (time_ms >= CCX_MAX_PERIOD)
5257 time_ms = CCX_MAX_PERIOD;
5258
5259 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD;
5260
5261 if (quotient < 4)
5262 idx = RTW89_CCX_4_US;
5263 else if (quotient < 8)
5264 idx = RTW89_CCX_8_US;
5265 else if (quotient < 16)
5266 idx = RTW89_CCX_16_US;
5267 else
5268 idx = RTW89_CCX_32_US;
5269
5270 *unit_idx = idx;
5271 *period = (time_ms * MS_TO_4US_RATIO) >> idx;
5272
5273 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5274 "[Trigger Time] period:%d, unit_idx:%d\n",
5275 *period, *unit_idx);
5276 }
5277
rtw89_phy_ccx_racing_release(struct rtw89_dev * rtwdev)5278 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev)
5279 {
5280 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5281
5282 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5283 "lv:(%d)->(0)\n", env->ccx_rac_lv);
5284
5285 env->ccx_ongoing = false;
5286 env->ccx_rac_lv = RTW89_RAC_RELEASE;
5287 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5288 }
5289
rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)5290 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev,
5291 struct rtw89_ccx_para_info *para)
5292 {
5293 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5294 bool is_update = env->ifs_clm_app != para->ifs_clm_app;
5295 u8 i = 0;
5296 u16 *ifs_th_l = env->ifs_clm_th_l;
5297 u16 *ifs_th_h = env->ifs_clm_th_h;
5298 u32 ifs_th0_us = 0, ifs_th_times = 0;
5299 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0};
5300
5301 if (!is_update)
5302 goto ifs_update_finished;
5303
5304 switch (para->ifs_clm_app) {
5305 case RTW89_IFS_CLM_INIT:
5306 case RTW89_IFS_CLM_BACKGROUND:
5307 case RTW89_IFS_CLM_ACS:
5308 case RTW89_IFS_CLM_DBG:
5309 case RTW89_IFS_CLM_DIG:
5310 case RTW89_IFS_CLM_TDMA_DIG:
5311 ifs_th0_us = IFS_CLM_TH0_UPPER;
5312 ifs_th_times = IFS_CLM_TH_MUL;
5313 break;
5314 case RTW89_IFS_CLM_DBG_MANUAL:
5315 ifs_th0_us = para->ifs_clm_manual_th0;
5316 ifs_th_times = para->ifs_clm_manual_th_times;
5317 break;
5318 default:
5319 break;
5320 }
5321
5322 /* Set sampling threshold for 4 different regions, unit in idx_cnt.
5323 * low[i] = high[i-1] + 1
5324 * high[i] = high[i-1] * ifs_th_times
5325 */
5326 ifs_th_l[IFS_CLM_TH_START_IDX] = 0;
5327 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us;
5328 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev,
5329 ifs_th0_us);
5330 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) {
5331 ifs_th_l[i] = ifs_th_h[i - 1] + 1;
5332 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times;
5333 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]);
5334 }
5335
5336 ifs_update_finished:
5337 if (!is_update)
5338 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5339 "No need to update IFS_TH\n");
5340
5341 return is_update;
5342 }
5343
rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev * rtwdev)5344 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev)
5345 {
5346 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5347 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5348 const struct rtw89_ccx_regs *ccx = phy->ccx;
5349 u8 i = 0;
5350
5351 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask,
5352 env->ifs_clm_th_l[0]);
5353 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask,
5354 env->ifs_clm_th_l[1]);
5355 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask,
5356 env->ifs_clm_th_l[2]);
5357 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask,
5358 env->ifs_clm_th_l[3]);
5359
5360 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask,
5361 env->ifs_clm_th_h[0]);
5362 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask,
5363 env->ifs_clm_th_h[1]);
5364 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask,
5365 env->ifs_clm_th_h[2]);
5366 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask,
5367 env->ifs_clm_th_h[3]);
5368
5369 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5370 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5371 "Update IFS_T%d_th{low, high} : {%d, %d}\n",
5372 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]);
5373 }
5374
rtw89_phy_ifs_clm_setting_init(struct rtw89_dev * rtwdev)5375 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev)
5376 {
5377 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5378 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5379 const struct rtw89_ccx_regs *ccx = phy->ccx;
5380 struct rtw89_ccx_para_info para = {0};
5381
5382 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5383 env->ifs_clm_mntr_time = 0;
5384
5385 para.ifs_clm_app = RTW89_IFS_CLM_INIT;
5386 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶))
5387 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
5388
5389 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true);
5390 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true);
5391 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true);
5392 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true);
5393 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true);
5394 }
5395
rtw89_phy_ccx_racing_ctrl(struct rtw89_dev * rtwdev,enum rtw89_env_racing_lv level)5396 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev,
5397 enum rtw89_env_racing_lv level)
5398 {
5399 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5400 int ret = 0;
5401
5402 if (level >= RTW89_RAC_MAX_NUM) {
5403 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5404 "[WARNING] Wrong LV=%d\n", level);
5405 return -EINVAL;
5406 }
5407
5408 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5409 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing,
5410 env->ccx_rac_lv, level);
5411
5412 if (env->ccx_ongoing) {
5413 if (level <= env->ccx_rac_lv)
5414 ret = -EINVAL;
5415 else
5416 env->ccx_ongoing = false;
5417 }
5418
5419 if (ret == 0)
5420 env->ccx_rac_lv = level;
5421
5422 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n",
5423 !ret);
5424
5425 return ret;
5426 }
5427
rtw89_phy_ccx_trigger(struct rtw89_dev * rtwdev)5428 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev)
5429 {
5430 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5431 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5432 const struct rtw89_ccx_regs *ccx = phy->ccx;
5433
5434 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0);
5435 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0);
5436 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1);
5437 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1);
5438
5439 env->ccx_ongoing = true;
5440 }
5441
rtw89_phy_ifs_clm_get_utility(struct rtw89_dev * rtwdev)5442 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev)
5443 {
5444 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5445 u8 i = 0;
5446 u32 res = 0;
5447
5448 env->ifs_clm_tx_ratio =
5449 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT);
5450 env->ifs_clm_edcca_excl_cca_ratio =
5451 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca,
5452 PERCENT);
5453 env->ifs_clm_cck_fa_ratio =
5454 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT);
5455 env->ifs_clm_ofdm_fa_ratio =
5456 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT);
5457 env->ifs_clm_cck_cca_excl_fa_ratio =
5458 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa,
5459 PERCENT);
5460 env->ifs_clm_ofdm_cca_excl_fa_ratio =
5461 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa,
5462 PERCENT);
5463 env->ifs_clm_cck_fa_permil =
5464 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL);
5465 env->ifs_clm_ofdm_fa_permil =
5466 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL);
5467
5468 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) {
5469 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) {
5470 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD;
5471 } else {
5472 env->ifs_clm_ifs_avg[i] =
5473 rtw89_phy_ccx_idx_to_us(rtwdev,
5474 env->ifs_clm_avg[i]);
5475 }
5476
5477 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]);
5478 res += env->ifs_clm_his[i] >> 1;
5479 if (env->ifs_clm_his[i])
5480 res /= env->ifs_clm_his[i];
5481 else
5482 res = 0;
5483 env->ifs_clm_cca_avg[i] = res;
5484 }
5485
5486 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5487 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5488 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio);
5489 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5490 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n",
5491 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio);
5492 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5493 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n",
5494 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil);
5495 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5496 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n",
5497 env->ifs_clm_cck_cca_excl_fa_ratio,
5498 env->ifs_clm_ofdm_cca_excl_fa_ratio);
5499 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5500 "Time:[his, ifs_avg(us), cca_avg(us)]\n");
5501 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5502 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n",
5503 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i],
5504 env->ifs_clm_cca_avg[i]);
5505 }
5506
rtw89_phy_ifs_clm_get_result(struct rtw89_dev * rtwdev)5507 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev)
5508 {
5509 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5510 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5511 const struct rtw89_ccx_regs *ccx = phy->ccx;
5512 u8 i = 0;
5513
5514 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5515 ccx->ifs_cnt_done_mask) == 0) {
5516 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5517 "Get IFS_CLM report Fail\n");
5518 return false;
5519 }
5520
5521 env->ifs_clm_tx =
5522 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5523 ccx->ifs_clm_tx_cnt_msk);
5524 env->ifs_clm_edcca_excl_cca =
5525 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr,
5526 ccx->ifs_clm_edcca_excl_cca_fa_mask);
5527 env->ifs_clm_cckcca_excl_fa =
5528 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5529 ccx->ifs_clm_cckcca_excl_fa_mask);
5530 env->ifs_clm_ofdmcca_excl_fa =
5531 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr,
5532 ccx->ifs_clm_ofdmcca_excl_fa_mask);
5533 env->ifs_clm_cckfa =
5534 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5535 ccx->ifs_clm_cck_fa_mask);
5536 env->ifs_clm_ofdmfa =
5537 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr,
5538 ccx->ifs_clm_ofdm_fa_mask);
5539
5540 env->ifs_clm_his[0] =
5541 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5542 ccx->ifs_t1_his_mask);
5543 env->ifs_clm_his[1] =
5544 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5545 ccx->ifs_t2_his_mask);
5546 env->ifs_clm_his[2] =
5547 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5548 ccx->ifs_t3_his_mask);
5549 env->ifs_clm_his[3] =
5550 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr,
5551 ccx->ifs_t4_his_mask);
5552
5553 env->ifs_clm_avg[0] =
5554 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5555 ccx->ifs_t1_avg_mask);
5556 env->ifs_clm_avg[1] =
5557 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr,
5558 ccx->ifs_t2_avg_mask);
5559 env->ifs_clm_avg[2] =
5560 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5561 ccx->ifs_t3_avg_mask);
5562 env->ifs_clm_avg[3] =
5563 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr,
5564 ccx->ifs_t4_avg_mask);
5565
5566 env->ifs_clm_cca[0] =
5567 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5568 ccx->ifs_t1_cca_mask);
5569 env->ifs_clm_cca[1] =
5570 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr,
5571 ccx->ifs_t2_cca_mask);
5572 env->ifs_clm_cca[2] =
5573 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5574 ccx->ifs_t3_cca_mask);
5575 env->ifs_clm_cca[3] =
5576 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr,
5577 ccx->ifs_t4_cca_mask);
5578
5579 env->ifs_clm_total_ifs =
5580 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr,
5581 ccx->ifs_total_mask);
5582
5583 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n",
5584 env->ifs_clm_total_ifs);
5585 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5586 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n",
5587 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca);
5588 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5589 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n",
5590 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa);
5591 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5592 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n",
5593 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa);
5594
5595 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n");
5596 for (i = 0; i < RTW89_IFS_CLM_NUM; i++)
5597 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5598 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i],
5599 env->ifs_clm_avg[i], env->ifs_clm_cca[i]);
5600
5601 rtw89_phy_ifs_clm_get_utility(rtwdev);
5602
5603 return true;
5604 }
5605
rtw89_phy_ifs_clm_set(struct rtw89_dev * rtwdev,struct rtw89_ccx_para_info * para)5606 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev,
5607 struct rtw89_ccx_para_info *para)
5608 {
5609 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5610 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5611 const struct rtw89_ccx_regs *ccx = phy->ccx;
5612 u32 period = 0;
5613 u32 unit_idx = 0;
5614
5615 if (para->mntr_time == 0) {
5616 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5617 "[WARN] MNTR_TIME is 0\n");
5618 return -EINVAL;
5619 }
5620
5621 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv))
5622 return -EINVAL;
5623
5624 if (para->mntr_time != env->ifs_clm_mntr_time) {
5625 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time,
5626 &period, &unit_idx);
5627 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5628 ccx->ifs_clm_period_mask, period);
5629 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr,
5630 ccx->ifs_clm_cnt_unit_mask,
5631 unit_idx);
5632
5633 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5634 "Update IFS-CLM time ((%d)) -> ((%d))\n",
5635 env->ifs_clm_mntr_time, para->mntr_time);
5636
5637 env->ifs_clm_mntr_time = para->mntr_time;
5638 env->ccx_period = (u16)period;
5639 env->ccx_unit_idx = (u8)unit_idx;
5640 }
5641
5642 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) {
5643 env->ifs_clm_app = para->ifs_clm_app;
5644 rtw89_phy_ifs_clm_set_th_reg(rtwdev);
5645 }
5646
5647 return 0;
5648 }
5649
rtw89_phy_env_monitor_track(struct rtw89_dev * rtwdev)5650 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev)
5651 {
5652 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
5653 struct rtw89_ccx_para_info para = {0};
5654 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5655
5656 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL;
5657 if (env->ccx_manual_ctrl) {
5658 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5659 "CCX in manual ctrl\n");
5660 return;
5661 }
5662
5663 /* only ifs_clm for now */
5664 if (rtw89_phy_ifs_clm_get_result(rtwdev))
5665 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5666
5667 rtw89_phy_ccx_racing_release(rtwdev);
5668 para.mntr_time = 1900;
5669 para.rac_lv = RTW89_RAC_LV_1;
5670 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND;
5671
5672 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0)
5673 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM;
5674 if (chk_result)
5675 rtw89_phy_ccx_trigger(rtwdev);
5676
5677 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK,
5678 "get_result=0x%x, chk_result:0x%x\n",
5679 env->ccx_watchdog_result, chk_result);
5680 }
5681
rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap * ie_page)5682 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page)
5683 {
5684 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM ||
5685 *ie_page == RTW89_RSVD_9)
5686 return false;
5687 else if (*ie_page > RTW89_RSVD_9)
5688 *ie_page -= 1;
5689
5690 return true;
5691 }
5692
rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)5693 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page)
5694 {
5695 static const u8 ie_page_shift = 2;
5696
5697 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift);
5698 }
5699
rtw89_physts_get_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,enum rtw89_phy_idx phy_idx)5700 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev,
5701 enum rtw89_phy_status_bitmap ie_page,
5702 enum rtw89_phy_idx phy_idx)
5703 {
5704 u32 addr;
5705
5706 if (!rtw89_physts_ie_page_valid(&ie_page))
5707 return 0;
5708
5709 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5710
5711 return rtw89_phy_read32_idx(rtwdev, addr, MASKDWORD, phy_idx);
5712 }
5713
rtw89_physts_set_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap ie_page,u32 val,enum rtw89_phy_idx phy_idx)5714 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev,
5715 enum rtw89_phy_status_bitmap ie_page,
5716 u32 val, enum rtw89_phy_idx phy_idx)
5717 {
5718 const struct rtw89_chip_info *chip = rtwdev->chip;
5719 u32 addr;
5720
5721 if (!rtw89_physts_ie_page_valid(&ie_page))
5722 return;
5723
5724 if (chip->chip_id == RTL8852A)
5725 val &= B_PHY_STS_BITMAP_MSK_52A;
5726
5727 addr = rtw89_phy_get_ie_bitmap_addr(ie_page);
5728 rtw89_phy_write32_idx(rtwdev, addr, MASKDWORD, val, phy_idx);
5729 }
5730
rtw89_physts_enable_ie_bitmap(struct rtw89_dev * rtwdev,enum rtw89_phy_status_bitmap bitmap,enum rtw89_phy_status_ie_type ie,bool enable,enum rtw89_phy_idx phy_idx)5731 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev,
5732 enum rtw89_phy_status_bitmap bitmap,
5733 enum rtw89_phy_status_ie_type ie,
5734 bool enable, enum rtw89_phy_idx phy_idx)
5735 {
5736 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap, phy_idx);
5737
5738 if (enable)
5739 val |= BIT(ie);
5740 else
5741 val &= ~BIT(ie);
5742
5743 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val, phy_idx);
5744 }
5745
rtw89_physts_enable_fail_report(struct rtw89_dev * rtwdev,bool enable,enum rtw89_phy_idx phy_idx)5746 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev,
5747 bool enable,
5748 enum rtw89_phy_idx phy_idx)
5749 {
5750 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
5751 const struct rtw89_physts_regs *physts = phy->physts;
5752
5753 if (enable) {
5754 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5755 physts->dis_trigger_fail_mask, phy_idx);
5756 rtw89_phy_write32_idx_clr(rtwdev, physts->setting_addr,
5757 physts->dis_trigger_brk_mask, phy_idx);
5758 } else {
5759 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5760 physts->dis_trigger_fail_mask, phy_idx);
5761 rtw89_phy_write32_idx_set(rtwdev, physts->setting_addr,
5762 physts->dis_trigger_brk_mask, phy_idx);
5763 }
5764 }
5765
__rtw89_physts_parsing_init(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)5766 static void __rtw89_physts_parsing_init(struct rtw89_dev *rtwdev,
5767 enum rtw89_phy_idx phy_idx)
5768 {
5769 u8 i;
5770
5771 rtw89_physts_enable_fail_report(rtwdev, false, phy_idx);
5772
5773 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) {
5774 if (i >= RTW89_CCK_PKT)
5775 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5776 RTW89_PHYSTS_IE09_FTR_0,
5777 true, phy_idx);
5778 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) ||
5779 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT))
5780 continue;
5781 rtw89_physts_enable_ie_bitmap(rtwdev, i,
5782 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A,
5783 true, phy_idx);
5784 }
5785 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT,
5786 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx);
5787 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT,
5788 RTW89_PHYSTS_IE13_DL_MU_DEF, true, phy_idx);
5789
5790 /* force IE01 for channel index, only channel field is valid */
5791 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT,
5792 RTW89_PHYSTS_IE01_CMN_OFDM, true, phy_idx);
5793 }
5794
rtw89_physts_parsing_init(struct rtw89_dev * rtwdev)5795 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev)
5796 {
5797 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_0);
5798 if (rtwdev->dbcc_en)
5799 __rtw89_physts_parsing_init(rtwdev, RTW89_PHY_1);
5800 }
5801
rtw89_phy_dig_read_gain_table(struct rtw89_dev * rtwdev,int type)5802 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type)
5803 {
5804 const struct rtw89_chip_info *chip = rtwdev->chip;
5805 struct rtw89_dig_info *dig = &rtwdev->dig;
5806 const struct rtw89_phy_dig_gain_cfg *cfg;
5807 const char *msg;
5808 u8 i;
5809 s8 gain_base;
5810 s8 *gain_arr;
5811 u32 tmp;
5812
5813 switch (type) {
5814 case RTW89_DIG_GAIN_LNA_G:
5815 gain_arr = dig->lna_gain_g;
5816 gain_base = LNA0_GAIN;
5817 cfg = chip->dig_table->cfg_lna_g;
5818 msg = "lna_gain_g";
5819 break;
5820 case RTW89_DIG_GAIN_TIA_G:
5821 gain_arr = dig->tia_gain_g;
5822 gain_base = TIA0_GAIN_G;
5823 cfg = chip->dig_table->cfg_tia_g;
5824 msg = "tia_gain_g";
5825 break;
5826 case RTW89_DIG_GAIN_LNA_A:
5827 gain_arr = dig->lna_gain_a;
5828 gain_base = LNA0_GAIN;
5829 cfg = chip->dig_table->cfg_lna_a;
5830 msg = "lna_gain_a";
5831 break;
5832 case RTW89_DIG_GAIN_TIA_A:
5833 gain_arr = dig->tia_gain_a;
5834 gain_base = TIA0_GAIN_A;
5835 cfg = chip->dig_table->cfg_tia_a;
5836 msg = "tia_gain_a";
5837 break;
5838 default:
5839 return;
5840 }
5841
5842 for (i = 0; i < cfg->size; i++) {
5843 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr,
5844 cfg->table[i].mask);
5845 tmp >>= DIG_GAIN_SHIFT;
5846 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base;
5847 gain_base += DIG_GAIN;
5848
5849 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n",
5850 msg, i, gain_arr[i]);
5851 }
5852 }
5853
rtw89_phy_dig_update_gain_para(struct rtw89_dev * rtwdev)5854 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev)
5855 {
5856 struct rtw89_dig_info *dig = &rtwdev->dig;
5857 u32 tmp;
5858 u8 i;
5859
5860 if (!rtwdev->hal.support_igi)
5861 return;
5862
5863 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW,
5864 B_PATH0_IB_PKPW_MSK);
5865 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT);
5866 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK,
5867 B_PATH0_IB_PBK_MSK);
5868 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n",
5869 dig->ib_pkpwr, dig->ib_pbk);
5870
5871 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++)
5872 rtw89_phy_dig_read_gain_table(rtwdev, i);
5873 }
5874
5875 static const u8 rssi_nolink = 22;
5876 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104};
5877 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88};
5878 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16};
5879 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528};
5880
rtw89_phy_dig_update_rssi_info(struct rtw89_dev * rtwdev)5881 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev)
5882 {
5883 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
5884 struct rtw89_dig_info *dig = &rtwdev->dig;
5885 bool is_linked = rtwdev->total_sta_assoc > 0;
5886
5887 if (is_linked) {
5888 dig->igi_rssi = ch_info->rssi_min >> 1;
5889 } else {
5890 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n");
5891 dig->igi_rssi = rssi_nolink;
5892 }
5893 }
5894
rtw89_phy_dig_update_para(struct rtw89_dev * rtwdev)5895 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev)
5896 {
5897 struct rtw89_dig_info *dig = &rtwdev->dig;
5898 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
5899 bool is_linked = rtwdev->total_sta_assoc > 0;
5900 const u16 *fa_th_src = NULL;
5901
5902 switch (chan->band_type) {
5903 case RTW89_BAND_2G:
5904 dig->lna_gain = dig->lna_gain_g;
5905 dig->tia_gain = dig->tia_gain_g;
5906 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink;
5907 dig->force_gaincode_idx_en = false;
5908 dig->dyn_pd_th_en = true;
5909 break;
5910 case RTW89_BAND_5G:
5911 default:
5912 dig->lna_gain = dig->lna_gain_a;
5913 dig->tia_gain = dig->tia_gain_a;
5914 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink;
5915 dig->force_gaincode_idx_en = true;
5916 dig->dyn_pd_th_en = true;
5917 break;
5918 }
5919 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th));
5920 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th));
5921 }
5922
5923 static const u8 pd_low_th_offset = 16, dynamic_igi_min = 0x20;
5924 static const u8 igi_max_performance_mode = 0x5a;
5925 static const u8 dynamic_pd_threshold_max;
5926
rtw89_phy_dig_para_reset(struct rtw89_dev * rtwdev)5927 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev)
5928 {
5929 struct rtw89_dig_info *dig = &rtwdev->dig;
5930
5931 dig->cur_gaincode.lna_idx = LNA_IDX_MAX;
5932 dig->cur_gaincode.tia_idx = TIA_IDX_MAX;
5933 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX;
5934 dig->force_gaincode.lna_idx = LNA_IDX_MAX;
5935 dig->force_gaincode.tia_idx = TIA_IDX_MAX;
5936 dig->force_gaincode.rxb_idx = RXB_IDX_MAX;
5937
5938 dig->dyn_igi_max = igi_max_performance_mode;
5939 dig->dyn_igi_min = dynamic_igi_min;
5940 dig->dyn_pd_th_max = dynamic_pd_threshold_max;
5941 dig->pd_low_th_ofst = pd_low_th_offset;
5942 dig->is_linked_pre = false;
5943 }
5944
rtw89_phy_dig_init(struct rtw89_dev * rtwdev)5945 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev)
5946 {
5947 rtw89_phy_dig_update_gain_para(rtwdev);
5948 rtw89_phy_dig_reset(rtwdev);
5949 }
5950
rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)5951 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
5952 {
5953 struct rtw89_dig_info *dig = &rtwdev->dig;
5954 u8 lna_idx;
5955
5956 if (rssi < dig->igi_rssi_th[0])
5957 lna_idx = RTW89_DIG_GAIN_LNA_IDX6;
5958 else if (rssi < dig->igi_rssi_th[1])
5959 lna_idx = RTW89_DIG_GAIN_LNA_IDX5;
5960 else if (rssi < dig->igi_rssi_th[2])
5961 lna_idx = RTW89_DIG_GAIN_LNA_IDX4;
5962 else if (rssi < dig->igi_rssi_th[3])
5963 lna_idx = RTW89_DIG_GAIN_LNA_IDX3;
5964 else if (rssi < dig->igi_rssi_th[4])
5965 lna_idx = RTW89_DIG_GAIN_LNA_IDX2;
5966 else
5967 lna_idx = RTW89_DIG_GAIN_LNA_IDX1;
5968
5969 return lna_idx;
5970 }
5971
rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi)5972 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi)
5973 {
5974 struct rtw89_dig_info *dig = &rtwdev->dig;
5975 u8 tia_idx;
5976
5977 if (rssi < dig->igi_rssi_th[0])
5978 tia_idx = RTW89_DIG_GAIN_TIA_IDX1;
5979 else
5980 tia_idx = RTW89_DIG_GAIN_TIA_IDX0;
5981
5982 return tia_idx;
5983 }
5984
5985 #define IB_PBK_BASE 110
5986 #define WB_RSSI_BASE 10
rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)5987 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
5988 struct rtw89_agc_gaincode_set *set)
5989 {
5990 struct rtw89_dig_info *dig = &rtwdev->dig;
5991 s8 lna_gain = dig->lna_gain[set->lna_idx];
5992 s8 tia_gain = dig->tia_gain[set->tia_idx];
5993 s32 wb_rssi = rssi + lna_gain + tia_gain;
5994 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE;
5995 u8 rxb_idx;
5996
5997 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi;
5998 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX);
5999
6000 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n",
6001 wb_rssi, rxb_idx_tmp);
6002
6003 return rxb_idx;
6004 }
6005
rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev * rtwdev,u8 rssi,struct rtw89_agc_gaincode_set * set)6006 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi,
6007 struct rtw89_agc_gaincode_set *set)
6008 {
6009 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi);
6010 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi);
6011 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set);
6012
6013 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6014 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n",
6015 rssi, set->lna_idx, set->tia_idx, set->rxb_idx);
6016 }
6017
6018 #define IGI_OFFSET_MAX 25
6019 #define IGI_OFFSET_MUL 2
rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev * rtwdev)6020 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev)
6021 {
6022 struct rtw89_dig_info *dig = &rtwdev->dig;
6023 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor;
6024 enum rtw89_dig_noisy_level noisy_lv;
6025 u8 igi_offset = dig->fa_rssi_ofst;
6026 u16 fa_ratio = 0;
6027
6028 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil;
6029
6030 if (fa_ratio < dig->fa_th[0])
6031 noisy_lv = RTW89_DIG_NOISY_LEVEL0;
6032 else if (fa_ratio < dig->fa_th[1])
6033 noisy_lv = RTW89_DIG_NOISY_LEVEL1;
6034 else if (fa_ratio < dig->fa_th[2])
6035 noisy_lv = RTW89_DIG_NOISY_LEVEL2;
6036 else if (fa_ratio < dig->fa_th[3])
6037 noisy_lv = RTW89_DIG_NOISY_LEVEL3;
6038 else
6039 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX;
6040
6041 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2)
6042 igi_offset = 0;
6043 else
6044 igi_offset += noisy_lv * IGI_OFFSET_MUL;
6045
6046 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX);
6047 dig->fa_rssi_ofst = igi_offset;
6048
6049 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6050 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n",
6051 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]);
6052
6053 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6054 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n",
6055 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil,
6056 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil,
6057 noisy_lv, igi_offset);
6058 }
6059
rtw89_phy_dig_set_lna_idx(struct rtw89_dev * rtwdev,u8 lna_idx)6060 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx)
6061 {
6062 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6063
6064 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr,
6065 dig_regs->p0_lna_init.mask, lna_idx);
6066 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr,
6067 dig_regs->p1_lna_init.mask, lna_idx);
6068 }
6069
rtw89_phy_dig_set_tia_idx(struct rtw89_dev * rtwdev,u8 tia_idx)6070 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx)
6071 {
6072 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6073
6074 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr,
6075 dig_regs->p0_tia_init.mask, tia_idx);
6076 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr,
6077 dig_regs->p1_tia_init.mask, tia_idx);
6078 }
6079
rtw89_phy_dig_set_rxb_idx(struct rtw89_dev * rtwdev,u8 rxb_idx)6080 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx)
6081 {
6082 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6083
6084 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr,
6085 dig_regs->p0_rxb_init.mask, rxb_idx);
6086 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr,
6087 dig_regs->p1_rxb_init.mask, rxb_idx);
6088 }
6089
rtw89_phy_dig_set_igi_cr(struct rtw89_dev * rtwdev,const struct rtw89_agc_gaincode_set set)6090 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev,
6091 const struct rtw89_agc_gaincode_set set)
6092 {
6093 if (!rtwdev->hal.support_igi)
6094 return;
6095
6096 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx);
6097 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx);
6098 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx);
6099
6100 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n",
6101 set.lna_idx, set.tia_idx, set.rxb_idx);
6102 }
6103
rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev * rtwdev,bool enable)6104 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev,
6105 bool enable)
6106 {
6107 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6108
6109 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr,
6110 dig_regs->p0_p20_pagcugc_en.mask, enable);
6111 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr,
6112 dig_regs->p0_s20_pagcugc_en.mask, enable);
6113 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr,
6114 dig_regs->p1_p20_pagcugc_en.mask, enable);
6115 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr,
6116 dig_regs->p1_s20_pagcugc_en.mask, enable);
6117
6118 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable);
6119 }
6120
rtw89_phy_dig_config_igi(struct rtw89_dev * rtwdev)6121 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev)
6122 {
6123 struct rtw89_dig_info *dig = &rtwdev->dig;
6124
6125 if (!rtwdev->hal.support_igi)
6126 return;
6127
6128 if (dig->force_gaincode_idx_en) {
6129 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
6130 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6131 "Force gaincode index enabled.\n");
6132 } else {
6133 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi,
6134 &dig->cur_gaincode);
6135 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode);
6136 }
6137 }
6138
rtw89_phy_dig_dyn_pd_th(struct rtw89_dev * rtwdev,u8 rssi,bool enable)6139 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi,
6140 bool enable)
6141 {
6142 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0);
6143 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs;
6144 enum rtw89_bandwidth cbw = chan->band_width;
6145 struct rtw89_dig_info *dig = &rtwdev->dig;
6146 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst;
6147 u8 ofdm_cca_th;
6148 s8 cck_cca_th;
6149 u32 pd_val = 0;
6150
6151 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX)
6152 under_region += PD_TH_SB_FLTR_CMP_VAL;
6153
6154 switch (cbw) {
6155 case RTW89_CHANNEL_WIDTH_40:
6156 under_region += PD_TH_BW40_CMP_VAL;
6157 break;
6158 case RTW89_CHANNEL_WIDTH_80:
6159 under_region += PD_TH_BW80_CMP_VAL;
6160 break;
6161 case RTW89_CHANNEL_WIDTH_160:
6162 under_region += PD_TH_BW160_CMP_VAL;
6163 break;
6164 case RTW89_CHANNEL_WIDTH_20:
6165 fallthrough;
6166 default:
6167 under_region += PD_TH_BW20_CMP_VAL;
6168 break;
6169 }
6170
6171 dig->dyn_pd_th_max = dig->igi_rssi;
6172
6173 final_rssi = min_t(u8, rssi, dig->igi_rssi);
6174 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region,
6175 PD_TH_MAX_RSSI + under_region);
6176
6177 if (enable) {
6178 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1;
6179 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6180 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n",
6181 final_rssi, ofdm_cca_th, under_region, pd_val);
6182 } else {
6183 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6184 "Dynamic PD th disabled, Set PD_low_bd=0\n");
6185 }
6186
6187 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
6188 dig_regs->pd_lower_bound_mask, pd_val);
6189 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg,
6190 dig_regs->pd_spatial_reuse_en, enable);
6191
6192 if (!rtwdev->hal.support_cckpd)
6193 return;
6194
6195 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI);
6196 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX);
6197
6198 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6199 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n",
6200 final_rssi, cck_cca_th, under_region, pd_val);
6201
6202 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg,
6203 dig_regs->bmode_cca_rssi_limit_en, enable);
6204 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg,
6205 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val);
6206 }
6207
rtw89_phy_dig_reset(struct rtw89_dev * rtwdev)6208 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev)
6209 {
6210 struct rtw89_dig_info *dig = &rtwdev->dig;
6211
6212 dig->bypass_dig = false;
6213 rtw89_phy_dig_para_reset(rtwdev);
6214 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode);
6215 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false);
6216 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
6217 rtw89_phy_dig_update_para(rtwdev);
6218 }
6219
6220 #define IGI_RSSI_MIN 10
6221 #define ABS_IGI_MIN 0xc
rtw89_phy_dig(struct rtw89_dev * rtwdev)6222 void rtw89_phy_dig(struct rtw89_dev *rtwdev)
6223 {
6224 struct rtw89_dig_info *dig = &rtwdev->dig;
6225 bool is_linked = rtwdev->total_sta_assoc > 0;
6226 u8 igi_min;
6227
6228 if (unlikely(dig->bypass_dig)) {
6229 dig->bypass_dig = false;
6230 return;
6231 }
6232
6233 rtw89_phy_dig_update_rssi_info(rtwdev);
6234
6235 if (!dig->is_linked_pre && is_linked) {
6236 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n");
6237 rtw89_phy_dig_update_para(rtwdev);
6238 dig->igi_fa_rssi = dig->igi_rssi;
6239 } else if (dig->is_linked_pre && !is_linked) {
6240 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n");
6241 rtw89_phy_dig_update_para(rtwdev);
6242 dig->igi_fa_rssi = dig->igi_rssi;
6243 }
6244 dig->is_linked_pre = is_linked;
6245
6246 rtw89_phy_dig_igi_offset_by_env(rtwdev);
6247
6248 igi_min = max_t(int, dig->igi_rssi - IGI_RSSI_MIN, 0);
6249 dig->dyn_igi_max = min(igi_min + IGI_OFFSET_MAX, igi_max_performance_mode);
6250 dig->dyn_igi_min = max(igi_min, ABS_IGI_MIN);
6251
6252 if (dig->dyn_igi_max >= dig->dyn_igi_min) {
6253 dig->igi_fa_rssi += dig->fa_rssi_ofst;
6254 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min,
6255 dig->dyn_igi_max);
6256 } else {
6257 dig->igi_fa_rssi = dig->dyn_igi_max;
6258 }
6259
6260 rtw89_debug(rtwdev, RTW89_DBG_DIG,
6261 "rssi=%03d, dyn_joint(max,min)=(%d,%d), final_rssi=%d\n",
6262 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min,
6263 dig->igi_fa_rssi);
6264
6265 rtw89_phy_dig_config_igi(rtwdev);
6266
6267 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en);
6268
6269 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max)
6270 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true);
6271 else
6272 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false);
6273 }
6274
__rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link)6275 static void __rtw89_phy_tx_path_div_sta_iter(struct rtw89_dev *rtwdev,
6276 struct rtw89_sta_link *rtwsta_link)
6277 {
6278 struct rtw89_hal *hal = &rtwdev->hal;
6279 u8 rssi_a, rssi_b;
6280 u32 candidate;
6281
6282 rssi_a = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_A]);
6283 rssi_b = ewma_rssi_read(&rtwsta_link->rssi[RF_PATH_B]);
6284
6285 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH)
6286 candidate = RF_A;
6287 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH)
6288 candidate = RF_B;
6289 else
6290 return;
6291
6292 if (hal->antenna_tx == candidate)
6293 return;
6294
6295 hal->antenna_tx = candidate;
6296 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta_link);
6297
6298 if (hal->antenna_tx == RF_A) {
6299 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12);
6300 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11);
6301 } else if (hal->antenna_tx == RF_B) {
6302 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11);
6303 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12);
6304 }
6305 }
6306
rtw89_phy_tx_path_div_sta_iter(void * data,struct ieee80211_sta * sta)6307 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta)
6308 {
6309 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
6310 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
6311 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6312 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6313 struct rtw89_vif_link *rtwvif_link;
6314 struct rtw89_sta_link *rtwsta_link;
6315 unsigned int link_id;
6316 bool *done = data;
6317
6318 if (WARN(ieee80211_vif_is_mld(vif), "MLD mix path_div\n"))
6319 return;
6320
6321 if (sta->tdls)
6322 return;
6323
6324 if (*done)
6325 return;
6326
6327 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) {
6328 rtwvif_link = rtwsta_link->rtwvif_link;
6329 if (rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION)
6330 continue;
6331
6332 *done = true;
6333 __rtw89_phy_tx_path_div_sta_iter(rtwdev, rtwsta_link);
6334 return;
6335 }
6336 }
6337
rtw89_phy_tx_path_div_track(struct rtw89_dev * rtwdev)6338 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev)
6339 {
6340 struct rtw89_hal *hal = &rtwdev->hal;
6341 bool done = false;
6342
6343 if (!hal->tx_path_diversity)
6344 return;
6345
6346 ieee80211_iterate_stations_atomic(rtwdev->hw,
6347 rtw89_phy_tx_path_div_sta_iter,
6348 &done);
6349 }
6350
6351 #define ANTDIV_MAIN 0
6352 #define ANTDIV_AUX 1
6353
rtw89_phy_antdiv_set_ant(struct rtw89_dev * rtwdev)6354 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev)
6355 {
6356 struct rtw89_hal *hal = &rtwdev->hal;
6357 u8 default_ant, optional_ant;
6358
6359 if (!hal->ant_diversity || hal->antenna_tx == 0)
6360 return;
6361
6362 if (hal->antenna_tx == RF_B) {
6363 default_ant = ANTDIV_AUX;
6364 optional_ant = ANTDIV_MAIN;
6365 } else {
6366 default_ant = ANTDIV_MAIN;
6367 optional_ant = ANTDIV_AUX;
6368 }
6369
6370 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL,
6371 default_ant, RTW89_PHY_0);
6372 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI,
6373 default_ant, RTW89_PHY_0);
6374 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT,
6375 optional_ant, RTW89_PHY_0);
6376 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI,
6377 default_ant, RTW89_PHY_0);
6378 }
6379
rtw89_phy_swap_hal_antenna(struct rtw89_dev * rtwdev)6380 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev)
6381 {
6382 struct rtw89_hal *hal = &rtwdev->hal;
6383
6384 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A;
6385 hal->antenna_tx = hal->antenna_rx;
6386 }
6387
rtw89_phy_antdiv_decision_state(struct rtw89_dev * rtwdev)6388 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev)
6389 {
6390 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6391 struct rtw89_hal *hal = &rtwdev->hal;
6392 bool no_change = false;
6393 u8 main_rssi, aux_rssi;
6394 u8 main_evm, aux_evm;
6395 u32 candidate;
6396
6397 antdiv->get_stats = false;
6398 antdiv->training_count = 0;
6399
6400 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats);
6401 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats);
6402 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats);
6403 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats);
6404
6405 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH)
6406 candidate = RF_A;
6407 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH)
6408 candidate = RF_B;
6409 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
6410 candidate = RF_A;
6411 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH)
6412 candidate = RF_B;
6413 else
6414 no_change = true;
6415
6416 if (no_change) {
6417 /* swap back from training antenna to original */
6418 rtw89_phy_swap_hal_antenna(rtwdev);
6419 return;
6420 }
6421
6422 hal->antenna_tx = candidate;
6423 hal->antenna_rx = candidate;
6424 }
6425
rtw89_phy_antdiv_training_state(struct rtw89_dev * rtwdev)6426 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev)
6427 {
6428 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6429 u64 state_period;
6430
6431 if (antdiv->training_count % 2 == 0) {
6432 if (antdiv->training_count == 0)
6433 rtw89_phy_antdiv_sts_reset(rtwdev);
6434
6435 antdiv->get_stats = true;
6436 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL);
6437 } else {
6438 antdiv->get_stats = false;
6439 state_period = msecs_to_jiffies(ANTDIV_DELAY);
6440
6441 rtw89_phy_swap_hal_antenna(rtwdev);
6442 rtw89_phy_antdiv_set_ant(rtwdev);
6443 }
6444
6445 antdiv->training_count++;
6446 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work,
6447 state_period);
6448 }
6449
rtw89_phy_antdiv_work(struct work_struct * work)6450 void rtw89_phy_antdiv_work(struct work_struct *work)
6451 {
6452 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
6453 antdiv_work.work);
6454 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6455
6456 mutex_lock(&rtwdev->mutex);
6457
6458 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) {
6459 rtw89_phy_antdiv_training_state(rtwdev);
6460 } else {
6461 rtw89_phy_antdiv_decision_state(rtwdev);
6462 rtw89_phy_antdiv_set_ant(rtwdev);
6463 }
6464
6465 mutex_unlock(&rtwdev->mutex);
6466 }
6467
rtw89_phy_antdiv_track(struct rtw89_dev * rtwdev)6468 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev)
6469 {
6470 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv;
6471 struct rtw89_hal *hal = &rtwdev->hal;
6472 u8 rssi, rssi_pre;
6473
6474 if (!hal->ant_diversity || hal->ant_diversity_fixed)
6475 return;
6476
6477 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats);
6478 rssi_pre = antdiv->rssi_pre;
6479 antdiv->rssi_pre = rssi;
6480 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats);
6481
6482 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH)
6483 return;
6484
6485 antdiv->training_count = 0;
6486 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0);
6487 }
6488
rtw89_phy_env_monitor_init(struct rtw89_dev * rtwdev)6489 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev)
6490 {
6491 rtw89_phy_ccx_top_setting_init(rtwdev);
6492 rtw89_phy_ifs_clm_setting_init(rtwdev);
6493 }
6494
rtw89_phy_edcca_init(struct rtw89_dev * rtwdev)6495 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev)
6496 {
6497 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6498 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6499
6500 memset(edcca_bak, 0, sizeof(*edcca_bak));
6501
6502 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) {
6503 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0);
6504 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2);
6505 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1);
6506 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0);
6507 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0);
6508 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0);
6509 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0);
6510 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1);
6511 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1);
6512 }
6513
6514 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st,
6515 edcca_regs->tx_collision_t2r_st_mask, 0x29);
6516 }
6517
rtw89_phy_dm_init(struct rtw89_dev * rtwdev)6518 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev)
6519 {
6520 rtw89_phy_stat_init(rtwdev);
6521
6522 rtw89_chip_bb_sethw(rtwdev);
6523
6524 rtw89_phy_env_monitor_init(rtwdev);
6525 rtw89_physts_parsing_init(rtwdev);
6526 rtw89_phy_dig_init(rtwdev);
6527 rtw89_phy_cfo_init(rtwdev);
6528 rtw89_phy_bb_wrap_init(rtwdev);
6529 rtw89_phy_edcca_init(rtwdev);
6530 rtw89_phy_ch_info_init(rtwdev);
6531 rtw89_phy_ul_tb_info_init(rtwdev);
6532 rtw89_phy_antdiv_init(rtwdev);
6533 rtw89_chip_rfe_gpio(rtwdev);
6534 rtw89_phy_antdiv_set_ant(rtwdev);
6535
6536 rtw89_chip_rfk_hw_init(rtwdev);
6537 rtw89_phy_init_rf_nctl(rtwdev);
6538 rtw89_chip_rfk_init(rtwdev);
6539 rtw89_chip_set_txpwr_ctrl(rtwdev);
6540 rtw89_chip_power_trim(rtwdev);
6541 rtw89_chip_cfg_txrx_path(rtwdev);
6542 }
6543
rtw89_phy_dm_reinit(struct rtw89_dev * rtwdev)6544 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev)
6545 {
6546 rtw89_phy_env_monitor_init(rtwdev);
6547 rtw89_physts_parsing_init(rtwdev);
6548 }
6549
rtw89_phy_set_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6550 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
6551 struct rtw89_vif_link *rtwvif_link)
6552 {
6553 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6554 const struct rtw89_chip_info *chip = rtwdev->chip;
6555 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld;
6556 enum rtw89_phy_idx phy_idx = rtwvif_link->phy_idx;
6557 struct ieee80211_bss_conf *bss_conf;
6558 u8 bss_color;
6559
6560 rcu_read_lock();
6561
6562 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6563 if (!bss_conf->he_support || !vif->cfg.assoc) {
6564 rcu_read_unlock();
6565 return;
6566 }
6567
6568 bss_color = bss_conf->he_bss_color.color;
6569
6570 rcu_read_unlock();
6571
6572 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1,
6573 phy_idx);
6574 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT,
6575 bss_color, phy_idx);
6576 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID,
6577 vif->cfg.aid, phy_idx);
6578 }
6579
rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc * desc)6580 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc)
6581 {
6582 return desc->ch != 0;
6583 }
6584
rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc * desc,const struct rtw89_chan * chan)6585 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc,
6586 const struct rtw89_chan *chan)
6587 {
6588 if (!rfk_chan_validate_desc(desc))
6589 return false;
6590
6591 if (desc->ch != chan->channel)
6592 return false;
6593
6594 if (desc->has_band && desc->band != chan->band_type)
6595 return false;
6596
6597 if (desc->has_bw && desc->bw != chan->band_width)
6598 return false;
6599
6600 return true;
6601 }
6602
6603 struct rfk_chan_iter_data {
6604 const struct rtw89_rfk_chan_desc desc;
6605 unsigned int found;
6606 };
6607
rfk_chan_iter_search(const struct rtw89_chan * chan,void * data)6608 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data)
6609 {
6610 struct rfk_chan_iter_data *iter_data = data;
6611
6612 if (rfk_chan_is_equivalent(&iter_data->desc, chan))
6613 iter_data->found++;
6614
6615 return 0;
6616 }
6617
rtw89_rfk_chan_lookup(struct rtw89_dev * rtwdev,const struct rtw89_rfk_chan_desc * desc,u8 desc_nr,const struct rtw89_chan * target_chan)6618 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
6619 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
6620 const struct rtw89_chan *target_chan)
6621 {
6622 int sel = -1;
6623 u8 i;
6624
6625 for (i = 0; i < desc_nr; i++) {
6626 struct rfk_chan_iter_data iter_data = {
6627 .desc = desc[i],
6628 };
6629
6630 if (rfk_chan_is_equivalent(&desc[i], target_chan))
6631 return i;
6632
6633 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data);
6634 if (!iter_data.found && sel == -1)
6635 sel = i;
6636 }
6637
6638 if (sel == -1) {
6639 rtw89_debug(rtwdev, RTW89_DBG_RFK,
6640 "no idle rfk entry; force replace the first\n");
6641 sel = 0;
6642 }
6643
6644 return sel;
6645 }
6646 EXPORT_SYMBOL(rtw89_rfk_chan_lookup);
6647
6648 static void
_rfk_write_rf(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6649 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6650 {
6651 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data);
6652 }
6653
6654 static void
_rfk_write32_mask(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6655 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6656 {
6657 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
6658 }
6659
6660 static void
_rfk_write32_set(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6661 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6662 {
6663 rtw89_phy_write32_set(rtwdev, def->addr, def->mask);
6664 }
6665
6666 static void
_rfk_write32_clr(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6667 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6668 {
6669 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask);
6670 }
6671
6672 static void
_rfk_delay(struct rtw89_dev * rtwdev,const struct rtw89_reg5_def * def)6673 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def)
6674 {
6675 udelay(def->data);
6676 }
6677
6678 static void
6679 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = {
6680 [RTW89_RFK_F_WRF] = _rfk_write_rf,
6681 [RTW89_RFK_F_WM] = _rfk_write32_mask,
6682 [RTW89_RFK_F_WS] = _rfk_write32_set,
6683 [RTW89_RFK_F_WC] = _rfk_write32_clr,
6684 [RTW89_RFK_F_DELAY] = _rfk_delay,
6685 };
6686
6687 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM);
6688
6689 void
rtw89_rfk_parser(struct rtw89_dev * rtwdev,const struct rtw89_rfk_tbl * tbl)6690 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl)
6691 {
6692 const struct rtw89_reg5_def *p = tbl->defs;
6693 const struct rtw89_reg5_def *end = tbl->defs + tbl->size;
6694
6695 for (; p < end; p++)
6696 _rfk_handler[p->flag](rtwdev, p);
6697 }
6698 EXPORT_SYMBOL(rtw89_rfk_parser);
6699
6700 #define RTW89_TSSI_FAST_MODE_NUM 4
6701
6702 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = {
6703 {0xD934, 0xff0000},
6704 {0xD934, 0xff000000},
6705 {0xD938, 0xff},
6706 {0xD934, 0xff00},
6707 };
6708
6709 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = {
6710 {0xD930, 0xff0000},
6711 {0xD930, 0xff000000},
6712 {0xD934, 0xff},
6713 {0xD930, 0xff00},
6714 };
6715
6716 static
rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg,u32 val)6717 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev,
6718 enum rtw89_mac_idx mac_idx,
6719 enum rtw89_tssi_bandedge_cfg bandedge_cfg,
6720 u32 val)
6721 {
6722 const struct rtw89_reg_def *regs;
6723 u32 reg;
6724 int i;
6725
6726 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
6727 regs = rtw89_tssi_fastmode_regs_flat;
6728 else
6729 regs = rtw89_tssi_fastmode_regs_level;
6730
6731 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) {
6732 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6733 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val);
6734 }
6735 }
6736
6737 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = {
6738 {0xD91C, 0xff000000},
6739 {0xD920, 0xff},
6740 {0xD920, 0xff00},
6741 {0xD920, 0xff0000},
6742 {0xD920, 0xff000000},
6743 {0xD924, 0xff},
6744 {0xD924, 0xff00},
6745 {0xD914, 0xff000000},
6746 {0xD918, 0xff},
6747 {0xD918, 0xff00},
6748 {0xD918, 0xff0000},
6749 {0xD918, 0xff000000},
6750 {0xD91C, 0xff},
6751 {0xD91C, 0xff00},
6752 {0xD91C, 0xff0000},
6753 };
6754
6755 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = {
6756 {0xD910, 0xff},
6757 {0xD910, 0xff00},
6758 {0xD910, 0xff0000},
6759 {0xD910, 0xff000000},
6760 {0xD914, 0xff},
6761 {0xD914, 0xff00},
6762 {0xD914, 0xff0000},
6763 {0xD908, 0xff},
6764 {0xD908, 0xff00},
6765 {0xD908, 0xff0000},
6766 {0xD908, 0xff000000},
6767 {0xD90C, 0xff},
6768 {0xD90C, 0xff00},
6769 {0xD90C, 0xff0000},
6770 {0xD90C, 0xff000000},
6771 };
6772
rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_tssi_bandedge_cfg bandedge_cfg)6773 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
6774 enum rtw89_mac_idx mac_idx,
6775 enum rtw89_tssi_bandedge_cfg bandedge_cfg)
6776 {
6777 const struct rtw89_chip_info *chip = rtwdev->chip;
6778 const struct rtw89_reg_def *regs;
6779 const u32 *data;
6780 u32 reg;
6781 int i;
6782
6783 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM)
6784 return;
6785
6786 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT)
6787 regs = rtw89_tssi_bandedge_regs_flat;
6788 else
6789 regs = rtw89_tssi_bandedge_regs_level;
6790
6791 data = chip->tssi_dbw_table->data[bandedge_cfg];
6792
6793 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) {
6794 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx);
6795 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]);
6796 }
6797
6798 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx);
6799 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg);
6800
6801 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg,
6802 data[RTW89_TSSI_SBW20]);
6803 }
6804 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg);
6805
6806 static
6807 const u8 rtw89_ch_base_table[16] = {1, 0xff,
6808 36, 100, 132, 149, 0xff,
6809 1, 33, 65, 97, 129, 161, 193, 225, 0xff};
6810 #define RTW89_CH_BASE_IDX_2G 0
6811 #define RTW89_CH_BASE_IDX_5G_FIRST 2
6812 #define RTW89_CH_BASE_IDX_5G_LAST 5
6813 #define RTW89_CH_BASE_IDX_6G_FIRST 7
6814 #define RTW89_CH_BASE_IDX_6G_LAST 14
6815
6816 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4)
6817 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0)
6818
rtw89_encode_chan_idx(struct rtw89_dev * rtwdev,u8 central_ch,u8 band)6819 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band)
6820 {
6821 u8 chan_idx;
6822 u8 last, first;
6823 u8 idx;
6824
6825 switch (band) {
6826 case RTW89_BAND_2G:
6827 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) |
6828 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch);
6829 return chan_idx;
6830 case RTW89_BAND_5G:
6831 first = RTW89_CH_BASE_IDX_5G_FIRST;
6832 last = RTW89_CH_BASE_IDX_5G_LAST;
6833 break;
6834 case RTW89_BAND_6G:
6835 first = RTW89_CH_BASE_IDX_6G_FIRST;
6836 last = RTW89_CH_BASE_IDX_6G_LAST;
6837 break;
6838 default:
6839 rtw89_warn(rtwdev, "Unsupported band %d\n", band);
6840 return 0;
6841 }
6842
6843 for (idx = last; idx >= first; idx--)
6844 if (central_ch >= rtw89_ch_base_table[idx])
6845 break;
6846
6847 if (idx < first) {
6848 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch);
6849 return 0;
6850 }
6851
6852 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) |
6853 FIELD_PREP(RTW89_CH_OFFSET_MASK,
6854 (central_ch - rtw89_ch_base_table[idx]) >> 1);
6855 return chan_idx;
6856 }
6857 EXPORT_SYMBOL(rtw89_encode_chan_idx);
6858
rtw89_decode_chan_idx(struct rtw89_dev * rtwdev,u8 chan_idx,u8 * ch,enum nl80211_band * band)6859 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
6860 u8 *ch, enum nl80211_band *band)
6861 {
6862 u8 idx, offset;
6863
6864 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx);
6865 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx);
6866
6867 if (idx == RTW89_CH_BASE_IDX_2G) {
6868 *band = NL80211_BAND_2GHZ;
6869 *ch = offset;
6870 return;
6871 }
6872
6873 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ;
6874 *ch = rtw89_ch_base_table[idx] + (offset << 1);
6875 }
6876 EXPORT_SYMBOL(rtw89_decode_chan_idx);
6877
rtw89_phy_config_edcca(struct rtw89_dev * rtwdev,bool scan)6878 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan)
6879 {
6880 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6881 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
6882
6883 if (scan) {
6884 edcca_bak->a =
6885 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6886 edcca_regs->edcca_mask);
6887 edcca_bak->p =
6888 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level,
6889 edcca_regs->edcca_p_mask);
6890 edcca_bak->ppdu =
6891 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level,
6892 edcca_regs->ppdu_mask);
6893
6894 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6895 edcca_regs->edcca_mask, EDCCA_MAX);
6896 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6897 edcca_regs->edcca_p_mask, EDCCA_MAX);
6898 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6899 edcca_regs->ppdu_mask, EDCCA_MAX);
6900 } else {
6901 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6902 edcca_regs->edcca_mask,
6903 edcca_bak->a);
6904 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
6905 edcca_regs->edcca_p_mask,
6906 edcca_bak->p);
6907 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
6908 edcca_regs->ppdu_mask,
6909 edcca_bak->ppdu);
6910 }
6911 }
6912
rtw89_phy_edcca_log(struct rtw89_dev * rtwdev)6913 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev)
6914 {
6915 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
6916 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80;
6917 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80;
6918 u8 path, per20_bitmap;
6919 u8 pwdb[8];
6920 u32 tmp;
6921
6922 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA))
6923 return;
6924
6925 if (rtwdev->chip->chip_id == RTL8922A)
6926 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6927 edcca_regs->rpt_sel_be_mask, 0);
6928
6929 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6930 edcca_regs->rpt_sel_mask, 0);
6931 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6932 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK);
6933 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80);
6934 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40);
6935 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20);
6936 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20);
6937 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB);
6938 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1);
6939 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2);
6940 pwdb_fb = u32_get_bits(tmp, MASKBYTE3);
6941
6942 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6943 edcca_regs->rpt_sel_mask, 4);
6944 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6945 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1);
6946 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2);
6947
6948 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a,
6949 MASKBYTE0);
6950
6951 if (rtwdev->chip->chip_id == RTL8922A) {
6952 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6953 edcca_regs->rpt_sel_be_mask, 4);
6954 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6955 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
6956 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
6957 pwdb[2] = u32_get_bits(tmp, MASKBYTE1);
6958 pwdb[3] = u32_get_bits(tmp, MASKBYTE0);
6959
6960 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be,
6961 edcca_regs->rpt_sel_be_mask, 5);
6962 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b);
6963 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
6964 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
6965 pwdb[6] = u32_get_bits(tmp, MASKBYTE1);
6966 pwdb[7] = u32_get_bits(tmp, MASKBYTE0);
6967 } else {
6968 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6969 edcca_regs->rpt_sel_mask, 0);
6970 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6971 pwdb[0] = u32_get_bits(tmp, MASKBYTE3);
6972 pwdb[1] = u32_get_bits(tmp, MASKBYTE2);
6973
6974 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6975 edcca_regs->rpt_sel_mask, 1);
6976 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6977 pwdb[2] = u32_get_bits(tmp, MASKBYTE3);
6978 pwdb[3] = u32_get_bits(tmp, MASKBYTE2);
6979
6980 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6981 edcca_regs->rpt_sel_mask, 2);
6982 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6983 pwdb[4] = u32_get_bits(tmp, MASKBYTE3);
6984 pwdb[5] = u32_get_bits(tmp, MASKBYTE2);
6985
6986 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel,
6987 edcca_regs->rpt_sel_mask, 3);
6988 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a);
6989 pwdb[6] = u32_get_bits(tmp, MASKBYTE3);
6990 pwdb[7] = u32_get_bits(tmp, MASKBYTE2);
6991 }
6992
6993 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6994 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap);
6995
6996 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
6997 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n",
6998 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5],
6999 pwdb[6], pwdb[7]);
7000
7001 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7002 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n",
7003 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80);
7004
7005 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7006 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n",
7007 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80);
7008 }
7009
rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev * rtwdev)7010 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev)
7011 {
7012 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info;
7013 bool is_linked = rtwdev->total_sta_assoc > 0;
7014 u8 rssi_min = ch_info->rssi_min >> 1;
7015 u8 edcca_thre;
7016
7017 if (!is_linked) {
7018 edcca_thre = EDCCA_MAX;
7019 } else {
7020 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER -
7021 EDCCA_TH_REF;
7022 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB);
7023 }
7024
7025 return edcca_thre;
7026 }
7027
rtw89_phy_edcca_thre_calc(struct rtw89_dev * rtwdev)7028 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev)
7029 {
7030 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs;
7031 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak;
7032 u8 th;
7033
7034 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev);
7035 if (th == edcca_bak->th_old)
7036 return;
7037
7038 edcca_bak->th_old = th;
7039
7040 rtw89_debug(rtwdev, RTW89_DBG_EDCCA,
7041 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th);
7042
7043 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
7044 edcca_regs->edcca_mask, th);
7045 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level,
7046 edcca_regs->edcca_p_mask, th);
7047 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level,
7048 edcca_regs->ppdu_mask, th);
7049 }
7050
rtw89_phy_edcca_track(struct rtw89_dev * rtwdev)7051 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev)
7052 {
7053 struct rtw89_hal *hal = &rtwdev->hal;
7054
7055 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA))
7056 return;
7057
7058 rtw89_phy_edcca_thre_calc(rtwdev);
7059 rtw89_phy_edcca_log(rtwdev);
7060 }
7061
rtw89_phy_get_kpath(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7062 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
7063 enum rtw89_phy_idx phy_idx)
7064 {
7065 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7066 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7067 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7068
7069 switch (rtwdev->mlo_dbcc_mode) {
7070 case MLO_1_PLUS_1_1RF:
7071 if (phy_idx == RTW89_PHY_0)
7072 return RF_A;
7073 else
7074 return RF_B;
7075 case MLO_1_PLUS_1_2RF:
7076 if (phy_idx == RTW89_PHY_0)
7077 return RF_A;
7078 else
7079 return RF_D;
7080 case MLO_0_PLUS_2_1RF:
7081 case MLO_2_PLUS_0_1RF:
7082 /* for both PHY 0/1 */
7083 return RF_AB;
7084 case MLO_0_PLUS_2_2RF:
7085 case MLO_2_PLUS_0_2RF:
7086 case MLO_2_PLUS_2_2RF:
7087 default:
7088 if (phy_idx == RTW89_PHY_0)
7089 return RF_AB;
7090 else
7091 return RF_CD;
7092 }
7093 }
7094 EXPORT_SYMBOL(rtw89_phy_get_kpath);
7095
rtw89_phy_get_syn_sel(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)7096 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
7097 enum rtw89_phy_idx phy_idx)
7098 {
7099 rtw89_debug(rtwdev, RTW89_DBG_RFK,
7100 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n",
7101 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx);
7102
7103 switch (rtwdev->mlo_dbcc_mode) {
7104 case MLO_1_PLUS_1_1RF:
7105 if (phy_idx == RTW89_PHY_0)
7106 return RF_PATH_A;
7107 else
7108 return RF_PATH_B;
7109 case MLO_1_PLUS_1_2RF:
7110 if (phy_idx == RTW89_PHY_0)
7111 return RF_PATH_A;
7112 else
7113 return RF_PATH_D;
7114 case MLO_0_PLUS_2_1RF:
7115 case MLO_2_PLUS_0_1RF:
7116 if (phy_idx == RTW89_PHY_0)
7117 return RF_PATH_A;
7118 else
7119 return RF_PATH_B;
7120 case MLO_0_PLUS_2_2RF:
7121 case MLO_2_PLUS_0_2RF:
7122 case MLO_2_PLUS_2_2RF:
7123 default:
7124 if (phy_idx == RTW89_PHY_0)
7125 return RF_PATH_A;
7126 else
7127 return RF_PATH_C;
7128 }
7129 }
7130 EXPORT_SYMBOL(rtw89_phy_get_syn_sel);
7131
7132 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = {
7133 .setting_addr = R_CCX,
7134 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK,
7135 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK,
7136 .trig_opt_mask = B_CCX_TRIG_OPT_MSK,
7137 .en_mask = B_CCX_EN_MSK,
7138 .ifs_cnt_addr = R_IFS_COUNTER,
7139 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK,
7140 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK,
7141 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK,
7142 .ifs_collect_en_mask = B_IFS_COLLECT_EN,
7143 .ifs_t1_addr = R_IFS_T1,
7144 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK,
7145 .ifs_t1_en_mask = B_IFS_T1_EN_MSK,
7146 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK,
7147 .ifs_t2_addr = R_IFS_T2,
7148 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK,
7149 .ifs_t2_en_mask = B_IFS_T2_EN_MSK,
7150 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK,
7151 .ifs_t3_addr = R_IFS_T3,
7152 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK,
7153 .ifs_t3_en_mask = B_IFS_T3_EN_MSK,
7154 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK,
7155 .ifs_t4_addr = R_IFS_T4,
7156 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK,
7157 .ifs_t4_en_mask = B_IFS_T4_EN_MSK,
7158 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK,
7159 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT,
7160 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK,
7161 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK,
7162 .ifs_clm_cca_addr = R_IFS_CLM_CCA,
7163 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK,
7164 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK,
7165 .ifs_clm_fa_addr = R_IFS_CLM_FA,
7166 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK,
7167 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK,
7168 .ifs_his_addr = R_IFS_HIS,
7169 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK,
7170 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK,
7171 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK,
7172 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK,
7173 .ifs_avg_l_addr = R_IFS_AVG_L,
7174 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK,
7175 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK,
7176 .ifs_avg_h_addr = R_IFS_AVG_H,
7177 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK,
7178 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK,
7179 .ifs_cca_l_addr = R_IFS_CCA_L,
7180 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK,
7181 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK,
7182 .ifs_cca_h_addr = R_IFS_CCA_H,
7183 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK,
7184 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK,
7185 .ifs_total_addr = R_IFSCNT,
7186 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK,
7187 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK,
7188 };
7189
7190 static const struct rtw89_physts_regs rtw89_physts_regs_ax = {
7191 .setting_addr = R_PLCP_HISTOGRAM,
7192 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL,
7193 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK,
7194 };
7195
7196 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = {
7197 .comp = R_DCFO_WEIGHT,
7198 .weighting_mask = B_DCFO_WEIGHT_MSK,
7199 .comp_seg0 = R_DCFO_OPT,
7200 .valid_0_mask = B_DCFO_OPT_EN,
7201 };
7202
7203 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = {
7204 .cr_base = 0x10000,
7205 .ccx = &rtw89_ccx_regs_ax,
7206 .physts = &rtw89_physts_regs_ax,
7207 .cfo = &rtw89_cfo_regs_ax,
7208 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax,
7209 .config_bb_gain = rtw89_phy_config_bb_gain_ax,
7210 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax,
7211 .bb_wrap_init = NULL,
7212 .ch_info_init = NULL,
7213
7214 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax,
7215 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax,
7216 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax,
7217 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax,
7218 };
7219 EXPORT_SYMBOL(rtw89_phy_gen_ax);
7220