1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD9832 SPI DDS driver
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <asm/div64.h>
9
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/spi/spi.h>
18 #include <linux/sysfs.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22
23 #include "ad9832.h"
24
25 #include "dds.h"
26
27 /* Registers */
28
29 #define AD9832_FREQ0LL 0x0
30 #define AD9832_FREQ0HL 0x1
31 #define AD9832_FREQ0LM 0x2
32 #define AD9832_FREQ0HM 0x3
33 #define AD9832_FREQ1LL 0x4
34 #define AD9832_FREQ1HL 0x5
35 #define AD9832_FREQ1LM 0x6
36 #define AD9832_FREQ1HM 0x7
37 #define AD9832_PHASE0L 0x8
38 #define AD9832_PHASE0H 0x9
39 #define AD9832_PHASE1L 0xA
40 #define AD9832_PHASE1H 0xB
41 #define AD9832_PHASE2L 0xC
42 #define AD9832_PHASE2H 0xD
43 #define AD9832_PHASE3L 0xE
44 #define AD9832_PHASE3H 0xF
45
46 #define AD9832_PHASE_SYM 0x10
47 #define AD9832_FREQ_SYM 0x11
48 #define AD9832_PINCTRL_EN 0x12
49 #define AD9832_OUTPUT_EN 0x13
50
51 /* Command Control Bits */
52
53 #define AD9832_CMD_PHA8BITSW 0x1
54 #define AD9832_CMD_PHA16BITSW 0x0
55 #define AD9832_CMD_FRE8BITSW 0x3
56 #define AD9832_CMD_FRE16BITSW 0x2
57 #define AD9832_CMD_FPSELECT 0x6
58 #define AD9832_CMD_SYNCSELSRC 0x8
59 #define AD9832_CMD_SLEEPRESCLR 0xC
60
61 #define AD9832_FREQ BIT(11)
62 #define AD9832_PHASE(x) (((x) & 3) << 9)
63 #define AD9832_SYNC BIT(13)
64 #define AD9832_SELSRC BIT(12)
65 #define AD9832_SLEEP BIT(13)
66 #define AD9832_RESET BIT(12)
67 #define AD9832_CLR BIT(11)
68 #define CMD_SHIFT 12
69 #define ADD_SHIFT 8
70 #define AD9832_FREQ_BITS 32
71 #define AD9832_PHASE_BITS 12
72 #define RES_MASK(bits) ((1 << (bits)) - 1)
73
74 /**
75 * struct ad9832_state - driver instance specific data
76 * @spi: spi_device
77 * @avdd: supply regulator for the analog section
78 * @dvdd: supply regulator for the digital section
79 * @mclk: external master clock
80 * @ctrl_fp: cached frequency/phase control word
81 * @ctrl_ss: cached sync/selsrc control word
82 * @ctrl_src: cached sleep/reset/clr word
83 * @xfer: default spi transfer
84 * @msg: default spi message
85 * @freq_xfer: tuning word spi transfer
86 * @freq_msg: tuning word spi message
87 * @phase_xfer: tuning word spi transfer
88 * @phase_msg: tuning word spi message
89 * @lock: protect sensor state
90 * @data: spi transmit buffer
91 * @phase_data: tuning word spi transmit buffer
92 * @freq_data: tuning word spi transmit buffer
93 */
94
95 struct ad9832_state {
96 struct spi_device *spi;
97 struct regulator *avdd;
98 struct regulator *dvdd;
99 struct clk *mclk;
100 unsigned short ctrl_fp;
101 unsigned short ctrl_ss;
102 unsigned short ctrl_src;
103 struct spi_transfer xfer;
104 struct spi_message msg;
105 struct spi_transfer freq_xfer[4];
106 struct spi_message freq_msg;
107 struct spi_transfer phase_xfer[2];
108 struct spi_message phase_msg;
109 struct mutex lock; /* protect sensor state */
110 /*
111 * DMA (thus cache coherency maintenance) requires the
112 * transfer buffers to live in their own cache lines.
113 */
114 union {
115 __be16 freq_data[4];
116 __be16 phase_data[2];
117 __be16 data;
118 } __aligned(IIO_DMA_MINALIGN);
119 };
120
ad9832_calc_freqreg(unsigned long mclk,unsigned long fout)121 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
122 {
123 unsigned long long freqreg = (u64)fout *
124 (u64)((u64)1L << AD9832_FREQ_BITS);
125 do_div(freqreg, mclk);
126 return freqreg;
127 }
128
ad9832_write_frequency(struct ad9832_state * st,unsigned int addr,unsigned long fout)129 static int ad9832_write_frequency(struct ad9832_state *st,
130 unsigned int addr, unsigned long fout)
131 {
132 unsigned long clk_freq;
133 unsigned long regval;
134
135 clk_freq = clk_get_rate(st->mclk);
136
137 if (!clk_freq || fout > (clk_freq / 2))
138 return -EINVAL;
139
140 regval = ad9832_calc_freqreg(clk_freq, fout);
141
142 st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
143 (addr << ADD_SHIFT) |
144 ((regval >> 24) & 0xFF));
145 st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
146 ((addr - 1) << ADD_SHIFT) |
147 ((regval >> 16) & 0xFF));
148 st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
149 ((addr - 2) << ADD_SHIFT) |
150 ((regval >> 8) & 0xFF));
151 st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
152 ((addr - 3) << ADD_SHIFT) |
153 ((regval >> 0) & 0xFF));
154
155 return spi_sync(st->spi, &st->freq_msg);
156 }
157
ad9832_write_phase(struct ad9832_state * st,unsigned long addr,unsigned long phase)158 static int ad9832_write_phase(struct ad9832_state *st,
159 unsigned long addr, unsigned long phase)
160 {
161 if (phase >= BIT(AD9832_PHASE_BITS))
162 return -EINVAL;
163
164 st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
165 (addr << ADD_SHIFT) |
166 ((phase >> 8) & 0xFF));
167 st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
168 ((addr - 1) << ADD_SHIFT) |
169 (phase & 0xFF));
170
171 return spi_sync(st->spi, &st->phase_msg);
172 }
173
ad9832_write(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)174 static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
175 const char *buf, size_t len)
176 {
177 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
178 struct ad9832_state *st = iio_priv(indio_dev);
179 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
180 int ret;
181 unsigned long val;
182
183 ret = kstrtoul(buf, 10, &val);
184 if (ret)
185 goto error_ret;
186
187 mutex_lock(&st->lock);
188 switch ((u32)this_attr->address) {
189 case AD9832_FREQ0HM:
190 case AD9832_FREQ1HM:
191 ret = ad9832_write_frequency(st, this_attr->address, val);
192 break;
193 case AD9832_PHASE0H:
194 case AD9832_PHASE1H:
195 case AD9832_PHASE2H:
196 case AD9832_PHASE3H:
197 ret = ad9832_write_phase(st, this_attr->address, val);
198 break;
199 case AD9832_PINCTRL_EN:
200 if (val)
201 st->ctrl_ss &= ~AD9832_SELSRC;
202 else
203 st->ctrl_ss |= AD9832_SELSRC;
204 st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
205 st->ctrl_ss);
206 ret = spi_sync(st->spi, &st->msg);
207 break;
208 case AD9832_FREQ_SYM:
209 if (val == 1) {
210 st->ctrl_fp |= AD9832_FREQ;
211 } else if (val == 0) {
212 st->ctrl_fp &= ~AD9832_FREQ;
213 } else {
214 ret = -EINVAL;
215 break;
216 }
217 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
218 st->ctrl_fp);
219 ret = spi_sync(st->spi, &st->msg);
220 break;
221 case AD9832_PHASE_SYM:
222 if (val > 3) {
223 ret = -EINVAL;
224 break;
225 }
226
227 st->ctrl_fp &= ~AD9832_PHASE(3);
228 st->ctrl_fp |= AD9832_PHASE(val);
229
230 st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
231 st->ctrl_fp);
232 ret = spi_sync(st->spi, &st->msg);
233 break;
234 case AD9832_OUTPUT_EN:
235 if (val)
236 st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
237 AD9832_CLR);
238 else
239 st->ctrl_src |= AD9832_RESET;
240
241 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
242 st->ctrl_src);
243 ret = spi_sync(st->spi, &st->msg);
244 break;
245 default:
246 ret = -ENODEV;
247 }
248 mutex_unlock(&st->lock);
249
250 error_ret:
251 return ret ? ret : len;
252 }
253
254 /*
255 * see dds.h for further information
256 */
257
258 static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
259 static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
260 static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
261 static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
262
263 static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
264 static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
265 static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
266 static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
267 static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
268 ad9832_write, AD9832_PHASE_SYM);
269 static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
270
271 static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
272 ad9832_write, AD9832_PINCTRL_EN);
273 static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
274 ad9832_write, AD9832_OUTPUT_EN);
275
276 static struct attribute *ad9832_attributes[] = {
277 &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
278 &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
279 &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
280 &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
281 &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
282 &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
283 &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
284 &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
285 &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
286 &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
287 &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
288 &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
289 NULL,
290 };
291
292 static const struct attribute_group ad9832_attribute_group = {
293 .attrs = ad9832_attributes,
294 };
295
296 static const struct iio_info ad9832_info = {
297 .attrs = &ad9832_attribute_group,
298 };
299
ad9832_reg_disable(void * reg)300 static void ad9832_reg_disable(void *reg)
301 {
302 regulator_disable(reg);
303 }
304
ad9832_probe(struct spi_device * spi)305 static int ad9832_probe(struct spi_device *spi)
306 {
307 struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
308 struct iio_dev *indio_dev;
309 struct ad9832_state *st;
310 int ret;
311
312 if (!pdata) {
313 dev_dbg(&spi->dev, "no platform data?\n");
314 return -ENODEV;
315 }
316
317 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
318 if (!indio_dev)
319 return -ENOMEM;
320
321 st = iio_priv(indio_dev);
322
323 st->avdd = devm_regulator_get(&spi->dev, "avdd");
324 if (IS_ERR(st->avdd))
325 return PTR_ERR(st->avdd);
326
327 ret = regulator_enable(st->avdd);
328 if (ret) {
329 dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
330 return ret;
331 }
332
333 ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->avdd);
334 if (ret)
335 return ret;
336
337 st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
338 if (IS_ERR(st->dvdd))
339 return PTR_ERR(st->dvdd);
340
341 ret = regulator_enable(st->dvdd);
342 if (ret) {
343 dev_err(&spi->dev, "Failed to enable specified DVDD supply\n");
344 return ret;
345 }
346
347 ret = devm_add_action_or_reset(&spi->dev, ad9832_reg_disable, st->dvdd);
348 if (ret)
349 return ret;
350
351 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
352 if (IS_ERR(st->mclk))
353 return PTR_ERR(st->mclk);
354
355 st->spi = spi;
356 mutex_init(&st->lock);
357
358 indio_dev->name = spi_get_device_id(spi)->name;
359 indio_dev->info = &ad9832_info;
360 indio_dev->modes = INDIO_DIRECT_MODE;
361
362 /* Setup default messages */
363
364 st->xfer.tx_buf = &st->data;
365 st->xfer.len = 2;
366
367 spi_message_init(&st->msg);
368 spi_message_add_tail(&st->xfer, &st->msg);
369
370 st->freq_xfer[0].tx_buf = &st->freq_data[0];
371 st->freq_xfer[0].len = 2;
372 st->freq_xfer[0].cs_change = 1;
373 st->freq_xfer[1].tx_buf = &st->freq_data[1];
374 st->freq_xfer[1].len = 2;
375 st->freq_xfer[1].cs_change = 1;
376 st->freq_xfer[2].tx_buf = &st->freq_data[2];
377 st->freq_xfer[2].len = 2;
378 st->freq_xfer[2].cs_change = 1;
379 st->freq_xfer[3].tx_buf = &st->freq_data[3];
380 st->freq_xfer[3].len = 2;
381
382 spi_message_init(&st->freq_msg);
383 spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
384 spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
385 spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
386 spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
387
388 st->phase_xfer[0].tx_buf = &st->phase_data[0];
389 st->phase_xfer[0].len = 2;
390 st->phase_xfer[0].cs_change = 1;
391 st->phase_xfer[1].tx_buf = &st->phase_data[1];
392 st->phase_xfer[1].len = 2;
393
394 spi_message_init(&st->phase_msg);
395 spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
396 spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
397
398 st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
399 st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
400 st->ctrl_src);
401 ret = spi_sync(st->spi, &st->msg);
402 if (ret) {
403 dev_err(&spi->dev, "device init failed\n");
404 return ret;
405 }
406
407 ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
408 if (ret)
409 return ret;
410
411 ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
412 if (ret)
413 return ret;
414
415 ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
416 if (ret)
417 return ret;
418
419 ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
420 if (ret)
421 return ret;
422
423 ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
424 if (ret)
425 return ret;
426
427 ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
428 if (ret)
429 return ret;
430
431 return devm_iio_device_register(&spi->dev, indio_dev);
432 }
433
434 static const struct spi_device_id ad9832_id[] = {
435 {"ad9832", 0},
436 {"ad9835", 0},
437 {}
438 };
439 MODULE_DEVICE_TABLE(spi, ad9832_id);
440
441 static struct spi_driver ad9832_driver = {
442 .driver = {
443 .name = "ad9832",
444 },
445 .probe = ad9832_probe,
446 .id_table = ad9832_id,
447 };
448 module_spi_driver(ad9832_driver);
449
450 MODULE_AUTHOR("Michael Hennerich <[email protected]>");
451 MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
452 MODULE_LICENSE("GPL v2");
453