1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AD5933 AD5934 Impedance Converter, Network Analyzer
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/i2c.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/regulator/consumer.h>
17 #include <linux/sysfs.h>
18 #include <linux/types.h>
19
20 #include <linux/iio/buffer.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/kfifo_buf.h>
23 #include <linux/iio/sysfs.h>
24
25 /* AD5933/AD5934 Registers */
26 #define AD5933_REG_CONTROL_HB 0x80 /* R/W, 1 byte */
27 #define AD5933_REG_CONTROL_LB 0x81 /* R/W, 1 byte */
28 #define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
29 #define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
30 #define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
31 #define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
32 #define AD5933_REG_STATUS 0x8F /* R, 1 byte */
33 #define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
34 #define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
35 #define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
36
37 /* AD5933_REG_CONTROL_HB Bits */
38 #define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
39 #define AD5933_CTRL_START_SWEEP (0x2 << 4)
40 #define AD5933_CTRL_INC_FREQ (0x3 << 4)
41 #define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
42 #define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
43 #define AD5933_CTRL_POWER_DOWN (0xA << 4)
44 #define AD5933_CTRL_STANDBY (0xB << 4)
45
46 #define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
47 #define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
48 #define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
49 #define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
50 #define AD5933_CTRL_RANGE(x) ((x) << 1)
51
52 #define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
53 #define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
54
55 /* AD5933_REG_CONTROL_LB Bits */
56 #define AD5933_CTRL_RESET (0x1 << 4)
57 #define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
58 #define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
59
60 /* AD5933_REG_STATUS Bits */
61 #define AD5933_STAT_TEMP_VALID (0x1 << 0)
62 #define AD5933_STAT_DATA_VALID (0x1 << 1)
63 #define AD5933_STAT_SWEEP_DONE (0x1 << 2)
64
65 /* I2C Block Commands */
66 #define AD5933_I2C_BLOCK_WRITE 0xA0
67 #define AD5933_I2C_BLOCK_READ 0xA1
68 #define AD5933_I2C_ADDR_POINTER 0xB0
69
70 /* Device Specs */
71 #define AD5933_INT_OSC_FREQ_Hz 16776000
72 #define AD5933_MAX_OUTPUT_FREQ_Hz 100000
73 #define AD5933_MAX_RETRIES 100
74
75 #define AD5933_OUT_RANGE 1
76 #define AD5933_OUT_RANGE_AVAIL 2
77 #define AD5933_OUT_SETTLING_CYCLES 3
78 #define AD5933_IN_PGA_GAIN 4
79 #define AD5933_IN_PGA_GAIN_AVAIL 5
80 #define AD5933_FREQ_POINTS 6
81
82 #define AD5933_POLL_TIME_ms 10
83 #define AD5933_INIT_EXCITATION_TIME_ms 100
84
85 struct ad5933_state {
86 struct i2c_client *client;
87 struct clk *mclk;
88 struct delayed_work work;
89 struct mutex lock; /* Protect sensor state */
90 unsigned long mclk_hz;
91 unsigned char ctrl_hb;
92 unsigned char ctrl_lb;
93 unsigned int range_avail[4];
94 unsigned short vref_mv;
95 unsigned short settling_cycles;
96 unsigned short freq_points;
97 unsigned int freq_start;
98 unsigned int freq_inc;
99 unsigned int state;
100 unsigned int poll_time_jiffies;
101 };
102
103 #define AD5933_CHANNEL(_type, _extend_name, _info_mask_separate, _address, \
104 _scan_index, _realbits) { \
105 .type = (_type), \
106 .extend_name = (_extend_name), \
107 .info_mask_separate = (_info_mask_separate), \
108 .address = (_address), \
109 .scan_index = (_scan_index), \
110 .scan_type = { \
111 .sign = 's', \
112 .realbits = (_realbits), \
113 .storagebits = 16, \
114 }, \
115 }
116
117 static const struct iio_chan_spec ad5933_channels[] = {
118 AD5933_CHANNEL(IIO_TEMP, NULL, BIT(IIO_CHAN_INFO_RAW) |
119 BIT(IIO_CHAN_INFO_SCALE), AD5933_REG_TEMP_DATA, -1, 14),
120 /* Ring Channels */
121 AD5933_CHANNEL(IIO_VOLTAGE, "real", 0, AD5933_REG_REAL_DATA, 0, 16),
122 AD5933_CHANNEL(IIO_VOLTAGE, "imag", 0, AD5933_REG_IMAG_DATA, 1, 16),
123 };
124
ad5933_i2c_write(struct i2c_client * client,u8 reg,u8 len,u8 * data)125 static int ad5933_i2c_write(struct i2c_client *client, u8 reg, u8 len, u8 *data)
126 {
127 int ret;
128
129 while (len--) {
130 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
131 if (ret < 0) {
132 dev_err(&client->dev, "I2C write error\n");
133 return ret;
134 }
135 }
136 return 0;
137 }
138
ad5933_i2c_read(struct i2c_client * client,u8 reg,u8 len,u8 * data)139 static int ad5933_i2c_read(struct i2c_client *client, u8 reg, u8 len, u8 *data)
140 {
141 int ret;
142
143 while (len--) {
144 ret = i2c_smbus_read_byte_data(client, reg++);
145 if (ret < 0) {
146 dev_err(&client->dev, "I2C read error\n");
147 return ret;
148 }
149 *data++ = ret;
150 }
151 return 0;
152 }
153
ad5933_cmd(struct ad5933_state * st,unsigned char cmd)154 static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
155 {
156 unsigned char dat = st->ctrl_hb | cmd;
157
158 return ad5933_i2c_write(st->client,
159 AD5933_REG_CONTROL_HB, 1, &dat);
160 }
161
ad5933_reset(struct ad5933_state * st)162 static int ad5933_reset(struct ad5933_state *st)
163 {
164 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
165
166 return ad5933_i2c_write(st->client,
167 AD5933_REG_CONTROL_LB, 1, &dat);
168 }
169
ad5933_wait_busy(struct ad5933_state * st,unsigned char event)170 static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
171 {
172 unsigned char val, timeout = AD5933_MAX_RETRIES;
173 int ret;
174
175 while (timeout--) {
176 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
177 if (ret < 0)
178 return ret;
179 if (val & event)
180 return val;
181 cpu_relax();
182 mdelay(1);
183 }
184
185 return -EAGAIN;
186 }
187
ad5933_set_freq(struct ad5933_state * st,unsigned int reg,unsigned long freq)188 static int ad5933_set_freq(struct ad5933_state *st,
189 unsigned int reg, unsigned long freq)
190 {
191 unsigned long long freqreg;
192 union {
193 __be32 d32;
194 u8 d8[4];
195 } dat;
196
197 freqreg = (u64)freq * (u64)(1 << 27);
198 do_div(freqreg, st->mclk_hz / 4);
199
200 switch (reg) {
201 case AD5933_REG_FREQ_START:
202 st->freq_start = freq;
203 break;
204 case AD5933_REG_FREQ_INC:
205 st->freq_inc = freq;
206 break;
207 default:
208 return -EINVAL;
209 }
210
211 dat.d32 = cpu_to_be32(freqreg);
212 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
213 }
214
ad5933_setup(struct ad5933_state * st)215 static int ad5933_setup(struct ad5933_state *st)
216 {
217 __be16 dat;
218 int ret;
219
220 ret = ad5933_reset(st);
221 if (ret < 0)
222 return ret;
223
224 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
225 if (ret < 0)
226 return ret;
227
228 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
229 if (ret < 0)
230 return ret;
231
232 st->settling_cycles = 10;
233 dat = cpu_to_be16(st->settling_cycles);
234
235 ret = ad5933_i2c_write(st->client,
236 AD5933_REG_SETTLING_CYCLES,
237 2, (u8 *)&dat);
238 if (ret < 0)
239 return ret;
240
241 st->freq_points = 100;
242 dat = cpu_to_be16(st->freq_points);
243
244 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
245 }
246
ad5933_calc_out_ranges(struct ad5933_state * st)247 static void ad5933_calc_out_ranges(struct ad5933_state *st)
248 {
249 int i;
250 unsigned int normalized_3v3[4] = {1980, 198, 383, 970};
251
252 for (i = 0; i < 4; i++)
253 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
254 }
255
256 /*
257 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
258 */
259
ad5933_show_frequency(struct device * dev,struct device_attribute * attr,char * buf)260 static ssize_t ad5933_show_frequency(struct device *dev,
261 struct device_attribute *attr,
262 char *buf)
263 {
264 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
265 struct ad5933_state *st = iio_priv(indio_dev);
266 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
267 int ret;
268 unsigned long long freqreg;
269 union {
270 __be32 d32;
271 u8 d8[4];
272 } dat;
273
274 ret = iio_device_claim_direct_mode(indio_dev);
275 if (ret)
276 return ret;
277 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
278 iio_device_release_direct_mode(indio_dev);
279 if (ret < 0)
280 return ret;
281
282 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
283
284 freqreg = (u64)freqreg * (u64)(st->mclk_hz / 4);
285 do_div(freqreg, BIT(27));
286
287 return sprintf(buf, "%d\n", (int)freqreg);
288 }
289
ad5933_store_frequency(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)290 static ssize_t ad5933_store_frequency(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf,
293 size_t len)
294 {
295 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
296 struct ad5933_state *st = iio_priv(indio_dev);
297 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
298 unsigned long val;
299 int ret;
300
301 ret = kstrtoul(buf, 10, &val);
302 if (ret)
303 return ret;
304
305 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
306 return -EINVAL;
307
308 ret = iio_device_claim_direct_mode(indio_dev);
309 if (ret)
310 return ret;
311 ret = ad5933_set_freq(st, this_attr->address, val);
312 iio_device_release_direct_mode(indio_dev);
313
314 return ret ? ret : len;
315 }
316
317 static IIO_DEVICE_ATTR(out_altvoltage0_frequency_start, 0644,
318 ad5933_show_frequency,
319 ad5933_store_frequency,
320 AD5933_REG_FREQ_START);
321
322 static IIO_DEVICE_ATTR(out_altvoltage0_frequency_increment, 0644,
323 ad5933_show_frequency,
324 ad5933_store_frequency,
325 AD5933_REG_FREQ_INC);
326
ad5933_show(struct device * dev,struct device_attribute * attr,char * buf)327 static ssize_t ad5933_show(struct device *dev,
328 struct device_attribute *attr,
329 char *buf)
330 {
331 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
332 struct ad5933_state *st = iio_priv(indio_dev);
333 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
334 int ret = 0, len = 0;
335
336 mutex_lock(&st->lock);
337 switch ((u32)this_attr->address) {
338 case AD5933_OUT_RANGE:
339 len = sprintf(buf, "%u\n",
340 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
341 break;
342 case AD5933_OUT_RANGE_AVAIL:
343 len = sprintf(buf, "%u %u %u %u\n", st->range_avail[0],
344 st->range_avail[3], st->range_avail[2],
345 st->range_avail[1]);
346 break;
347 case AD5933_OUT_SETTLING_CYCLES:
348 len = sprintf(buf, "%d\n", st->settling_cycles);
349 break;
350 case AD5933_IN_PGA_GAIN:
351 len = sprintf(buf, "%s\n",
352 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
353 "1" : "0.2");
354 break;
355 case AD5933_IN_PGA_GAIN_AVAIL:
356 len = sprintf(buf, "1 0.2\n");
357 break;
358 case AD5933_FREQ_POINTS:
359 len = sprintf(buf, "%d\n", st->freq_points);
360 break;
361 default:
362 ret = -EINVAL;
363 }
364
365 mutex_unlock(&st->lock);
366 return ret ? ret : len;
367 }
368
ad5933_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)369 static ssize_t ad5933_store(struct device *dev,
370 struct device_attribute *attr,
371 const char *buf,
372 size_t len)
373 {
374 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
375 struct ad5933_state *st = iio_priv(indio_dev);
376 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
377 u16 val;
378 int i, ret = 0;
379 __be16 dat;
380
381 if (this_attr->address != AD5933_IN_PGA_GAIN) {
382 ret = kstrtou16(buf, 10, &val);
383 if (ret)
384 return ret;
385 }
386
387 ret = iio_device_claim_direct_mode(indio_dev);
388 if (ret)
389 return ret;
390 mutex_lock(&st->lock);
391 switch ((u32)this_attr->address) {
392 case AD5933_OUT_RANGE:
393 ret = -EINVAL;
394 for (i = 0; i < 4; i++)
395 if (val == st->range_avail[i]) {
396 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
397 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
398 ret = ad5933_cmd(st, 0);
399 break;
400 }
401 break;
402 case AD5933_IN_PGA_GAIN:
403 if (sysfs_streq(buf, "1")) {
404 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
405 } else if (sysfs_streq(buf, "0.2")) {
406 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
407 } else {
408 ret = -EINVAL;
409 break;
410 }
411 ret = ad5933_cmd(st, 0);
412 break;
413 case AD5933_OUT_SETTLING_CYCLES:
414 val = clamp(val, (u16)0, (u16)0x7FF);
415 st->settling_cycles = val;
416
417 /* 2x, 4x handling, see datasheet */
418 if (val > 1022)
419 val = (val >> 2) | (3 << 9);
420 else if (val > 511)
421 val = (val >> 1) | BIT(9);
422
423 dat = cpu_to_be16(val);
424 ret = ad5933_i2c_write(st->client,
425 AD5933_REG_SETTLING_CYCLES,
426 2, (u8 *)&dat);
427 break;
428 case AD5933_FREQ_POINTS:
429 val = clamp(val, (u16)0, (u16)511);
430 st->freq_points = val;
431
432 dat = cpu_to_be16(val);
433 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
434 (u8 *)&dat);
435 break;
436 default:
437 ret = -EINVAL;
438 }
439
440 mutex_unlock(&st->lock);
441 iio_device_release_direct_mode(indio_dev);
442 return ret ? ret : len;
443 }
444
445 static IIO_DEVICE_ATTR(out_altvoltage0_raw, 0644,
446 ad5933_show,
447 ad5933_store,
448 AD5933_OUT_RANGE);
449
450 static IIO_DEVICE_ATTR(out_altvoltage0_scale_available, 0444,
451 ad5933_show,
452 NULL,
453 AD5933_OUT_RANGE_AVAIL);
454
455 static IIO_DEVICE_ATTR(in_voltage0_scale, 0644,
456 ad5933_show,
457 ad5933_store,
458 AD5933_IN_PGA_GAIN);
459
460 static IIO_DEVICE_ATTR(in_voltage0_scale_available, 0444,
461 ad5933_show,
462 NULL,
463 AD5933_IN_PGA_GAIN_AVAIL);
464
465 static IIO_DEVICE_ATTR(out_altvoltage0_frequency_points, 0644,
466 ad5933_show,
467 ad5933_store,
468 AD5933_FREQ_POINTS);
469
470 static IIO_DEVICE_ATTR(out_altvoltage0_settling_cycles, 0644,
471 ad5933_show,
472 ad5933_store,
473 AD5933_OUT_SETTLING_CYCLES);
474
475 /*
476 * note:
477 * ideally we would handle the scale attributes via the iio_info
478 * (read|write)_raw methods, however this part is a untypical since we
479 * don't create dedicated sysfs channel attributes for out0 and in0.
480 */
481 static struct attribute *ad5933_attributes[] = {
482 &iio_dev_attr_out_altvoltage0_raw.dev_attr.attr,
483 &iio_dev_attr_out_altvoltage0_scale_available.dev_attr.attr,
484 &iio_dev_attr_out_altvoltage0_frequency_start.dev_attr.attr,
485 &iio_dev_attr_out_altvoltage0_frequency_increment.dev_attr.attr,
486 &iio_dev_attr_out_altvoltage0_frequency_points.dev_attr.attr,
487 &iio_dev_attr_out_altvoltage0_settling_cycles.dev_attr.attr,
488 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
489 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
490 NULL
491 };
492
493 static const struct attribute_group ad5933_attribute_group = {
494 .attrs = ad5933_attributes,
495 };
496
ad5933_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)497 static int ad5933_read_raw(struct iio_dev *indio_dev,
498 struct iio_chan_spec const *chan,
499 int *val,
500 int *val2,
501 long m)
502 {
503 struct ad5933_state *st = iio_priv(indio_dev);
504 __be16 dat;
505 int ret;
506
507 switch (m) {
508 case IIO_CHAN_INFO_RAW:
509 ret = iio_device_claim_direct_mode(indio_dev);
510 if (ret)
511 return ret;
512 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
513 if (ret < 0)
514 goto out;
515 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
516 if (ret < 0)
517 goto out;
518
519 ret = ad5933_i2c_read(st->client,
520 AD5933_REG_TEMP_DATA,
521 2, (u8 *)&dat);
522 if (ret < 0)
523 goto out;
524 iio_device_release_direct_mode(indio_dev);
525 *val = sign_extend32(be16_to_cpu(dat), 13);
526
527 return IIO_VAL_INT;
528 case IIO_CHAN_INFO_SCALE:
529 *val = 1000;
530 *val2 = 5;
531 return IIO_VAL_FRACTIONAL_LOG2;
532 }
533
534 return -EINVAL;
535 out:
536 iio_device_release_direct_mode(indio_dev);
537 return ret;
538 }
539
540 static const struct iio_info ad5933_info = {
541 .read_raw = ad5933_read_raw,
542 .attrs = &ad5933_attribute_group,
543 };
544
ad5933_ring_preenable(struct iio_dev * indio_dev)545 static int ad5933_ring_preenable(struct iio_dev *indio_dev)
546 {
547 struct ad5933_state *st = iio_priv(indio_dev);
548 int ret;
549
550 if (bitmap_empty(indio_dev->active_scan_mask,
551 iio_get_masklength(indio_dev)))
552 return -EINVAL;
553
554 ret = ad5933_reset(st);
555 if (ret < 0)
556 return ret;
557
558 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
559 if (ret < 0)
560 return ret;
561
562 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
563 if (ret < 0)
564 return ret;
565
566 st->state = AD5933_CTRL_INIT_START_FREQ;
567
568 return 0;
569 }
570
ad5933_ring_postenable(struct iio_dev * indio_dev)571 static int ad5933_ring_postenable(struct iio_dev *indio_dev)
572 {
573 struct ad5933_state *st = iio_priv(indio_dev);
574
575 /*
576 * AD5933_CTRL_INIT_START_FREQ:
577 * High Q complex circuits require a long time to reach steady state.
578 * To facilitate the measurement of such impedances, this mode allows
579 * the user full control of the settling time requirement before
580 * entering start frequency sweep mode where the impedance measurement
581 * takes place. In this mode the impedance is excited with the
582 * programmed start frequency (ad5933_ring_preenable),
583 * but no measurement takes place.
584 */
585
586 schedule_delayed_work(&st->work,
587 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
588 return 0;
589 }
590
ad5933_ring_postdisable(struct iio_dev * indio_dev)591 static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
592 {
593 struct ad5933_state *st = iio_priv(indio_dev);
594
595 cancel_delayed_work_sync(&st->work);
596 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
597 }
598
599 static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
600 .preenable = ad5933_ring_preenable,
601 .postenable = ad5933_ring_postenable,
602 .postdisable = ad5933_ring_postdisable,
603 };
604
ad5933_work(struct work_struct * work)605 static void ad5933_work(struct work_struct *work)
606 {
607 struct ad5933_state *st = container_of(work,
608 struct ad5933_state, work.work);
609 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
610 __be16 buf[2];
611 u16 val[2];
612 unsigned char status;
613 int ret;
614
615 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
616 /* start sweep */
617 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
618 st->state = AD5933_CTRL_START_SWEEP;
619 schedule_delayed_work(&st->work, st->poll_time_jiffies);
620 return;
621 }
622
623 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
624 if (ret)
625 return;
626
627 if (status & AD5933_STAT_DATA_VALID) {
628 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
629 iio_get_masklength(indio_dev));
630 ret = ad5933_i2c_read(st->client,
631 test_bit(1, indio_dev->active_scan_mask) ?
632 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
633 scan_count * 2, (u8 *)buf);
634 if (ret)
635 return;
636
637 if (scan_count == 2) {
638 val[0] = be16_to_cpu(buf[0]);
639 val[1] = be16_to_cpu(buf[1]);
640 } else {
641 val[0] = be16_to_cpu(buf[0]);
642 }
643 iio_push_to_buffers(indio_dev, val);
644 } else {
645 /* no data available - try again later */
646 schedule_delayed_work(&st->work, st->poll_time_jiffies);
647 return;
648 }
649
650 if (status & AD5933_STAT_SWEEP_DONE) {
651 /*
652 * last sample received - power down do
653 * nothing until the ring enable is toggled
654 */
655 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
656 } else {
657 /* we just received a valid datum, move on to the next */
658 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
659 schedule_delayed_work(&st->work, st->poll_time_jiffies);
660 }
661 }
662
ad5933_probe(struct i2c_client * client)663 static int ad5933_probe(struct i2c_client *client)
664 {
665 const struct i2c_device_id *id = i2c_client_get_device_id(client);
666 int ret;
667 struct ad5933_state *st;
668 struct iio_dev *indio_dev;
669 unsigned long ext_clk_hz = 0;
670
671 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
672 if (!indio_dev)
673 return -ENOMEM;
674
675 st = iio_priv(indio_dev);
676 i2c_set_clientdata(client, indio_dev);
677 st->client = client;
678
679 mutex_init(&st->lock);
680
681 ret = devm_regulator_get_enable_read_voltage(&client->dev, "vdd");
682 if (ret < 0)
683 return dev_err_probe(&client->dev, ret, "failed to get vdd voltage\n");
684
685 st->vref_mv = ret / 1000;
686
687 st->mclk = devm_clk_get_enabled(&client->dev, "mclk");
688 if (IS_ERR(st->mclk) && PTR_ERR(st->mclk) != -ENOENT)
689 return PTR_ERR(st->mclk);
690
691 if (!IS_ERR(st->mclk))
692 ext_clk_hz = clk_get_rate(st->mclk);
693
694 if (ext_clk_hz) {
695 st->mclk_hz = ext_clk_hz;
696 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
697 } else {
698 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
699 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
700 }
701
702 ad5933_calc_out_ranges(st);
703 INIT_DELAYED_WORK(&st->work, ad5933_work);
704 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
705
706 indio_dev->info = &ad5933_info;
707 indio_dev->name = id->name;
708 indio_dev->modes = INDIO_DIRECT_MODE;
709 indio_dev->channels = ad5933_channels;
710 indio_dev->num_channels = ARRAY_SIZE(ad5933_channels);
711
712 ret = devm_iio_kfifo_buffer_setup(&client->dev, indio_dev,
713 &ad5933_ring_setup_ops);
714 if (ret)
715 return ret;
716
717 ret = ad5933_setup(st);
718 if (ret)
719 return ret;
720
721 return devm_iio_device_register(&client->dev, indio_dev);
722 }
723
724 static const struct i2c_device_id ad5933_id[] = {
725 { "ad5933" },
726 { "ad5934" },
727 {}
728 };
729
730 MODULE_DEVICE_TABLE(i2c, ad5933_id);
731
732 static const struct of_device_id ad5933_of_match[] = {
733 { .compatible = "adi,ad5933" },
734 { .compatible = "adi,ad5934" },
735 { },
736 };
737
738 MODULE_DEVICE_TABLE(of, ad5933_of_match);
739
740 static struct i2c_driver ad5933_driver = {
741 .driver = {
742 .name = "ad5933",
743 .of_match_table = ad5933_of_match,
744 },
745 .probe = ad5933_probe,
746 .id_table = ad5933_id,
747 };
748 module_i2c_driver(ad5933_driver);
749
750 MODULE_AUTHOR("Michael Hennerich <[email protected]>");
751 MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
752 MODULE_LICENSE("GPL v2");
753