1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
4 * Caesar Wang <[email protected]>
5 */
6
7 #include <linux/clk.h>
8 #include <linux/delay.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/module.h>
12 #include <linux/of.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/reset.h>
18 #include <linux/thermal.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/pinctrl/consumer.h>
21
22 /*
23 * If the temperature over a period of time High,
24 * the resulting TSHUT gave CRU module,let it reset the entire chip,
25 * or via GPIO give PMIC.
26 */
27 enum tshut_mode {
28 TSHUT_MODE_CRU = 0,
29 TSHUT_MODE_GPIO,
30 };
31
32 /*
33 * The system Temperature Sensors tshut(tshut) polarity
34 * the bit 8 is tshut polarity.
35 * 0: low active, 1: high active
36 */
37 enum tshut_polarity {
38 TSHUT_LOW_ACTIVE = 0,
39 TSHUT_HIGH_ACTIVE,
40 };
41
42 /*
43 * The conversion table has the adc value and temperature.
44 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
45 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
46 */
47 enum adc_sort_mode {
48 ADC_DECREMENT = 0,
49 ADC_INCREMENT,
50 };
51
52 #include "thermal_hwmon.h"
53
54 /**
55 * struct chip_tsadc_table - hold information about chip-specific differences
56 * @id: conversion table
57 * @length: size of conversion table
58 * @data_mask: mask to apply on data inputs
59 * @mode: sort mode of this adc variant (incrementing or decrementing)
60 */
61 struct chip_tsadc_table {
62 const struct tsadc_table *id;
63 unsigned int length;
64 u32 data_mask;
65 enum adc_sort_mode mode;
66 };
67
68 /**
69 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
70 * @chn_offset: the channel offset of the first channel
71 * @chn_num: the channel number of tsadc chip
72 * @tshut_temp: the hardware-controlled shutdown temperature value
73 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
74 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
75 * @initialize: SoC special initialize tsadc controller method
76 * @irq_ack: clear the interrupt
77 * @control: enable/disable method for the tsadc controller
78 * @get_temp: get the temperature
79 * @set_alarm_temp: set the high temperature interrupt
80 * @set_tshut_temp: set the hardware-controlled shutdown temperature
81 * @set_tshut_mode: set the hardware-controlled shutdown mode
82 * @table: the chip-specific conversion table
83 */
84 struct rockchip_tsadc_chip {
85 /* The sensor id of chip correspond to the ADC channel */
86 int chn_offset;
87 int chn_num;
88
89 /* The hardware-controlled tshut property */
90 int tshut_temp;
91 enum tshut_mode tshut_mode;
92 enum tshut_polarity tshut_polarity;
93
94 /* Chip-wide methods */
95 void (*initialize)(struct regmap *grf,
96 void __iomem *reg, enum tshut_polarity p);
97 void (*irq_ack)(void __iomem *reg);
98 void (*control)(void __iomem *reg, bool on);
99
100 /* Per-sensor methods */
101 int (*get_temp)(const struct chip_tsadc_table *table,
102 int chn, void __iomem *reg, int *temp);
103 int (*set_alarm_temp)(const struct chip_tsadc_table *table,
104 int chn, void __iomem *reg, int temp);
105 int (*set_tshut_temp)(const struct chip_tsadc_table *table,
106 int chn, void __iomem *reg, int temp);
107 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
108
109 /* Per-table methods */
110 struct chip_tsadc_table table;
111 };
112
113 /**
114 * struct rockchip_thermal_sensor - hold the information of thermal sensor
115 * @thermal: pointer to the platform/configuration data
116 * @tzd: pointer to a thermal zone
117 * @id: identifier of the thermal sensor
118 */
119 struct rockchip_thermal_sensor {
120 struct rockchip_thermal_data *thermal;
121 struct thermal_zone_device *tzd;
122 int id;
123 };
124
125 /**
126 * struct rockchip_thermal_data - hold the private data of thermal driver
127 * @chip: pointer to the platform/configuration data
128 * @pdev: platform device of thermal
129 * @reset: the reset controller of tsadc
130 * @sensors: array of thermal sensors
131 * @clk: the controller clock is divided by the exteral 24MHz
132 * @pclk: the advanced peripherals bus clock
133 * @grf: the general register file will be used to do static set by software
134 * @regs: the base address of tsadc controller
135 * @tshut_temp: the hardware-controlled shutdown temperature value
136 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
137 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
138 */
139 struct rockchip_thermal_data {
140 const struct rockchip_tsadc_chip *chip;
141 struct platform_device *pdev;
142 struct reset_control *reset;
143
144 struct rockchip_thermal_sensor *sensors;
145
146 struct clk *clk;
147 struct clk *pclk;
148
149 struct regmap *grf;
150 void __iomem *regs;
151
152 int tshut_temp;
153 enum tshut_mode tshut_mode;
154 enum tshut_polarity tshut_polarity;
155 };
156
157 /*
158 * TSADC Sensor Register description:
159 *
160 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
161 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
162 *
163 */
164 #define TSADCV2_USER_CON 0x00
165 #define TSADCV2_AUTO_CON 0x04
166 #define TSADCV2_INT_EN 0x08
167 #define TSADCV2_INT_PD 0x0c
168 #define TSADCV3_AUTO_SRC_CON 0x0c
169 #define TSADCV3_HT_INT_EN 0x14
170 #define TSADCV3_HSHUT_GPIO_INT_EN 0x18
171 #define TSADCV3_HSHUT_CRU_INT_EN 0x1c
172 #define TSADCV3_INT_PD 0x24
173 #define TSADCV3_HSHUT_PD 0x28
174 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
175 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
176 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
177 #define TSADCV3_DATA(chn) (0x2c + (chn) * 0x04)
178 #define TSADCV3_COMP_INT(chn) (0x6c + (chn) * 0x04)
179 #define TSADCV3_COMP_SHUT(chn) (0x10c + (chn) * 0x04)
180 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
181 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
182 #define TSADCV3_HIGHT_INT_DEBOUNCE 0x14c
183 #define TSADCV3_HIGHT_TSHUT_DEBOUNCE 0x150
184 #define TSADCV2_AUTO_PERIOD 0x68
185 #define TSADCV2_AUTO_PERIOD_HT 0x6c
186 #define TSADCV3_AUTO_PERIOD 0x154
187 #define TSADCV3_AUTO_PERIOD_HT 0x158
188
189 #define TSADCV2_AUTO_EN BIT(0)
190 #define TSADCV2_AUTO_EN_MASK BIT(16)
191 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
192 #define TSADCV3_AUTO_SRC_EN(chn) BIT(chn)
193 #define TSADCV3_AUTO_SRC_EN_MASK(chn) BIT(16 + chn)
194 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
195 #define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
196
197 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
198
199 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
200 #define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
201 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
202 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
203
204 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
205 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
206 #define TSADCV4_INT_PD_CLEAR_MASK 0xffffffff
207
208 #define TSADCV2_DATA_MASK 0xfff
209 #define TSADCV3_DATA_MASK 0x3ff
210 #define TSADCV4_DATA_MASK 0x1ff
211
212 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
213 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
214 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
215 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
216 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
217 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
218
219 #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */
220 #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
221 #define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
222 #define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
223
224 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
225 #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
226
227 #define GRF_SARADC_TESTBIT 0x0e644
228 #define GRF_TSADC_TESTBIT_L 0x0e648
229 #define GRF_TSADC_TESTBIT_H 0x0e64c
230
231 #define PX30_GRF_SOC_CON2 0x0408
232
233 #define RK3568_GRF_TSADC_CON 0x0600
234 #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
235 #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
236 #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
237 #define RK3568_GRF_TSADC_TSEN (0x10001 << 8)
238
239 #define RK3588_GRF0_TSADC_CON 0x0100
240
241 #define RK3588_GRF0_TSADC_TRM (0xff0077 << 0)
242 #define RK3588_GRF0_TSADC_SHUT_2CRU (0x30003 << 10)
243 #define RK3588_GRF0_TSADC_SHUT_2GPIO (0x70007 << 12)
244
245 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
246 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
247 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
248 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
249
250 #define GRF_CON_TSADC_CH_INV (0x10001 << 1)
251
252 /**
253 * struct tsadc_table - code to temperature conversion table
254 * @code: the value of adc channel
255 * @temp: the temperature
256 * Note:
257 * code to temperature mapping of the temperature sensor is a piece wise linear
258 * curve.Any temperature, code faling between to 2 give temperatures can be
259 * linearly interpolated.
260 * Code to Temperature mapping should be updated based on manufacturer results.
261 */
262 struct tsadc_table {
263 u32 code;
264 int temp;
265 };
266
267 static const struct tsadc_table rv1108_table[] = {
268 {0, -40000},
269 {374, -40000},
270 {382, -35000},
271 {389, -30000},
272 {397, -25000},
273 {405, -20000},
274 {413, -15000},
275 {421, -10000},
276 {429, -5000},
277 {436, 0},
278 {444, 5000},
279 {452, 10000},
280 {460, 15000},
281 {468, 20000},
282 {476, 25000},
283 {483, 30000},
284 {491, 35000},
285 {499, 40000},
286 {507, 45000},
287 {515, 50000},
288 {523, 55000},
289 {531, 60000},
290 {539, 65000},
291 {547, 70000},
292 {555, 75000},
293 {562, 80000},
294 {570, 85000},
295 {578, 90000},
296 {586, 95000},
297 {594, 100000},
298 {602, 105000},
299 {610, 110000},
300 {618, 115000},
301 {626, 120000},
302 {634, 125000},
303 {TSADCV2_DATA_MASK, 125000},
304 };
305
306 static const struct tsadc_table rk3228_code_table[] = {
307 {0, -40000},
308 {588, -40000},
309 {593, -35000},
310 {598, -30000},
311 {603, -25000},
312 {608, -20000},
313 {613, -15000},
314 {618, -10000},
315 {623, -5000},
316 {629, 0},
317 {634, 5000},
318 {639, 10000},
319 {644, 15000},
320 {649, 20000},
321 {654, 25000},
322 {660, 30000},
323 {665, 35000},
324 {670, 40000},
325 {675, 45000},
326 {681, 50000},
327 {686, 55000},
328 {691, 60000},
329 {696, 65000},
330 {702, 70000},
331 {707, 75000},
332 {712, 80000},
333 {717, 85000},
334 {723, 90000},
335 {728, 95000},
336 {733, 100000},
337 {738, 105000},
338 {744, 110000},
339 {749, 115000},
340 {754, 120000},
341 {760, 125000},
342 {TSADCV2_DATA_MASK, 125000},
343 };
344
345 static const struct tsadc_table rk3288_code_table[] = {
346 {TSADCV2_DATA_MASK, -40000},
347 {3800, -40000},
348 {3792, -35000},
349 {3783, -30000},
350 {3774, -25000},
351 {3765, -20000},
352 {3756, -15000},
353 {3747, -10000},
354 {3737, -5000},
355 {3728, 0},
356 {3718, 5000},
357 {3708, 10000},
358 {3698, 15000},
359 {3688, 20000},
360 {3678, 25000},
361 {3667, 30000},
362 {3656, 35000},
363 {3645, 40000},
364 {3634, 45000},
365 {3623, 50000},
366 {3611, 55000},
367 {3600, 60000},
368 {3588, 65000},
369 {3575, 70000},
370 {3563, 75000},
371 {3550, 80000},
372 {3537, 85000},
373 {3524, 90000},
374 {3510, 95000},
375 {3496, 100000},
376 {3482, 105000},
377 {3467, 110000},
378 {3452, 115000},
379 {3437, 120000},
380 {3421, 125000},
381 {0, 125000},
382 };
383
384 static const struct tsadc_table rk3328_code_table[] = {
385 {0, -40000},
386 {296, -40000},
387 {304, -35000},
388 {313, -30000},
389 {322, -25000},
390 {331, -20000},
391 {340, -15000},
392 {349, -10000},
393 {359, -5000},
394 {368, 0},
395 {378, 5000},
396 {388, 10000},
397 {398, 15000},
398 {408, 20000},
399 {418, 25000},
400 {429, 30000},
401 {440, 35000},
402 {451, 40000},
403 {462, 45000},
404 {473, 50000},
405 {485, 55000},
406 {496, 60000},
407 {508, 65000},
408 {521, 70000},
409 {533, 75000},
410 {546, 80000},
411 {559, 85000},
412 {572, 90000},
413 {586, 95000},
414 {600, 100000},
415 {614, 105000},
416 {629, 110000},
417 {644, 115000},
418 {659, 120000},
419 {675, 125000},
420 {TSADCV2_DATA_MASK, 125000},
421 };
422
423 static const struct tsadc_table rk3368_code_table[] = {
424 {0, -40000},
425 {106, -40000},
426 {108, -35000},
427 {110, -30000},
428 {112, -25000},
429 {114, -20000},
430 {116, -15000},
431 {118, -10000},
432 {120, -5000},
433 {122, 0},
434 {124, 5000},
435 {126, 10000},
436 {128, 15000},
437 {130, 20000},
438 {132, 25000},
439 {134, 30000},
440 {136, 35000},
441 {138, 40000},
442 {140, 45000},
443 {142, 50000},
444 {144, 55000},
445 {146, 60000},
446 {148, 65000},
447 {150, 70000},
448 {152, 75000},
449 {154, 80000},
450 {156, 85000},
451 {158, 90000},
452 {160, 95000},
453 {162, 100000},
454 {163, 105000},
455 {165, 110000},
456 {167, 115000},
457 {169, 120000},
458 {171, 125000},
459 {TSADCV3_DATA_MASK, 125000},
460 };
461
462 static const struct tsadc_table rk3399_code_table[] = {
463 {0, -40000},
464 {402, -40000},
465 {410, -35000},
466 {419, -30000},
467 {427, -25000},
468 {436, -20000},
469 {444, -15000},
470 {453, -10000},
471 {461, -5000},
472 {470, 0},
473 {478, 5000},
474 {487, 10000},
475 {496, 15000},
476 {504, 20000},
477 {513, 25000},
478 {521, 30000},
479 {530, 35000},
480 {538, 40000},
481 {547, 45000},
482 {555, 50000},
483 {564, 55000},
484 {573, 60000},
485 {581, 65000},
486 {590, 70000},
487 {599, 75000},
488 {607, 80000},
489 {616, 85000},
490 {624, 90000},
491 {633, 95000},
492 {642, 100000},
493 {650, 105000},
494 {659, 110000},
495 {668, 115000},
496 {677, 120000},
497 {685, 125000},
498 {TSADCV3_DATA_MASK, 125000},
499 };
500
501 static const struct tsadc_table rk3568_code_table[] = {
502 {0, -40000},
503 {1584, -40000},
504 {1620, -35000},
505 {1652, -30000},
506 {1688, -25000},
507 {1720, -20000},
508 {1756, -15000},
509 {1788, -10000},
510 {1824, -5000},
511 {1856, 0},
512 {1892, 5000},
513 {1924, 10000},
514 {1956, 15000},
515 {1992, 20000},
516 {2024, 25000},
517 {2060, 30000},
518 {2092, 35000},
519 {2128, 40000},
520 {2160, 45000},
521 {2196, 50000},
522 {2228, 55000},
523 {2264, 60000},
524 {2300, 65000},
525 {2332, 70000},
526 {2368, 75000},
527 {2400, 80000},
528 {2436, 85000},
529 {2468, 90000},
530 {2500, 95000},
531 {2536, 100000},
532 {2572, 105000},
533 {2604, 110000},
534 {2636, 115000},
535 {2672, 120000},
536 {2704, 125000},
537 {TSADCV2_DATA_MASK, 125000},
538 };
539
540 static const struct tsadc_table rk3588_code_table[] = {
541 {0, -40000},
542 {215, -40000},
543 {285, 25000},
544 {350, 85000},
545 {395, 125000},
546 {TSADCV4_DATA_MASK, 125000},
547 };
548
rk_tsadcv2_temp_to_code(const struct chip_tsadc_table * table,int temp)549 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
550 int temp)
551 {
552 int high, low, mid;
553 unsigned long num;
554 unsigned int denom;
555 u32 error = table->data_mask;
556
557 low = 0;
558 high = (table->length - 1) - 1; /* ignore the last check for table */
559 mid = (high + low) / 2;
560
561 /* Return mask code data when the temp is over table range */
562 if (temp < table->id[low].temp || temp > table->id[high].temp)
563 goto exit;
564
565 while (low <= high) {
566 if (temp == table->id[mid].temp)
567 return table->id[mid].code;
568 else if (temp < table->id[mid].temp)
569 high = mid - 1;
570 else
571 low = mid + 1;
572 mid = (low + high) / 2;
573 }
574
575 /*
576 * The conversion code granularity provided by the table. Let's
577 * assume that the relationship between temperature and
578 * analog value between 2 table entries is linear and interpolate
579 * to produce less granular result.
580 */
581 num = abs(table->id[mid + 1].code - table->id[mid].code);
582 num *= temp - table->id[mid].temp;
583 denom = table->id[mid + 1].temp - table->id[mid].temp;
584
585 switch (table->mode) {
586 case ADC_DECREMENT:
587 return table->id[mid].code - (num / denom);
588 case ADC_INCREMENT:
589 return table->id[mid].code + (num / denom);
590 default:
591 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
592 return error;
593 }
594
595 exit:
596 pr_err("%s: invalid temperature, temp=%d error=%d\n",
597 __func__, temp, error);
598 return error;
599 }
600
rk_tsadcv2_code_to_temp(const struct chip_tsadc_table * table,u32 code,int * temp)601 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
602 u32 code, int *temp)
603 {
604 unsigned int low = 1;
605 unsigned int high = table->length - 1;
606 unsigned int mid = (low + high) / 2;
607 unsigned int num;
608 unsigned long denom;
609
610 WARN_ON(table->length < 2);
611
612 switch (table->mode) {
613 case ADC_DECREMENT:
614 code &= table->data_mask;
615 if (code <= table->id[high].code)
616 return -EAGAIN; /* Incorrect reading */
617
618 while (low <= high) {
619 if (code >= table->id[mid].code &&
620 code < table->id[mid - 1].code)
621 break;
622 else if (code < table->id[mid].code)
623 low = mid + 1;
624 else
625 high = mid - 1;
626
627 mid = (low + high) / 2;
628 }
629 break;
630 case ADC_INCREMENT:
631 code &= table->data_mask;
632 if (code < table->id[low].code)
633 return -EAGAIN; /* Incorrect reading */
634
635 while (low <= high) {
636 if (code <= table->id[mid].code &&
637 code > table->id[mid - 1].code)
638 break;
639 else if (code > table->id[mid].code)
640 low = mid + 1;
641 else
642 high = mid - 1;
643
644 mid = (low + high) / 2;
645 }
646 break;
647 default:
648 pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
649 return -EINVAL;
650 }
651
652 /*
653 * The 5C granularity provided by the table is too much. Let's
654 * assume that the relationship between sensor readings and
655 * temperature between 2 table entries is linear and interpolate
656 * to produce less granular result.
657 */
658 num = table->id[mid].temp - table->id[mid - 1].temp;
659 num *= abs(table->id[mid - 1].code - code);
660 denom = abs(table->id[mid - 1].code - table->id[mid].code);
661 *temp = table->id[mid - 1].temp + (num / denom);
662
663 return 0;
664 }
665
666 /**
667 * rk_tsadcv2_initialize - initialize TASDC Controller.
668 * @grf: the general register file will be used to do static set by software
669 * @regs: the base address of tsadc controller
670 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
671 *
672 * (1) Set TSADC_V2_AUTO_PERIOD:
673 * Configure the interleave between every two accessing of
674 * TSADC in normal operation.
675 *
676 * (2) Set TSADCV2_AUTO_PERIOD_HT:
677 * Configure the interleave between every two accessing of
678 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
679 *
680 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
681 * If the temperature is higher than COMP_INT or COMP_SHUT for
682 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
683 */
rk_tsadcv2_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)684 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
685 enum tshut_polarity tshut_polarity)
686 {
687 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
688 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
689 regs + TSADCV2_AUTO_CON);
690 else
691 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
692 regs + TSADCV2_AUTO_CON);
693
694 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
695 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
696 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
697 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
698 regs + TSADCV2_AUTO_PERIOD_HT);
699 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
700 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
701 }
702
703 /**
704 * rk_tsadcv3_initialize - initialize TASDC Controller.
705 * @grf: the general register file will be used to do static set by software
706 * @regs: the base address of tsadc controller
707 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
708 *
709 * (1) The tsadc control power sequence.
710 *
711 * (2) Set TSADC_V2_AUTO_PERIOD:
712 * Configure the interleave between every two accessing of
713 * TSADC in normal operation.
714 *
715 * (2) Set TSADCV2_AUTO_PERIOD_HT:
716 * Configure the interleave between every two accessing of
717 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
718 *
719 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
720 * If the temperature is higher than COMP_INT or COMP_SHUT for
721 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
722 */
rk_tsadcv3_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)723 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
724 enum tshut_polarity tshut_polarity)
725 {
726 /* The tsadc control power sequence */
727 if (IS_ERR(grf)) {
728 /* Set interleave value to workround ic time sync issue */
729 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
730 TSADCV2_USER_CON);
731
732 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
733 regs + TSADCV2_AUTO_PERIOD);
734 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
735 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
736 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
737 regs + TSADCV2_AUTO_PERIOD_HT);
738 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
739 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
740
741 } else {
742 /* Enable the voltage common mode feature */
743 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
744 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
745
746 usleep_range(15, 100); /* The spec note says at least 15 us */
747 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
748 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
749 usleep_range(90, 200); /* The spec note says at least 90 us */
750
751 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
752 regs + TSADCV2_AUTO_PERIOD);
753 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
754 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
755 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
756 regs + TSADCV2_AUTO_PERIOD_HT);
757 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
758 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
759 }
760
761 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
762 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
763 regs + TSADCV2_AUTO_CON);
764 else
765 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
766 regs + TSADCV2_AUTO_CON);
767 }
768
rk_tsadcv4_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)769 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
770 enum tshut_polarity tshut_polarity)
771 {
772 rk_tsadcv2_initialize(grf, regs, tshut_polarity);
773 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
774 }
775
rk_tsadcv7_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)776 static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
777 enum tshut_polarity tshut_polarity)
778 {
779 writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
780 writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
781 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
782 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
783 writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
784 regs + TSADCV2_AUTO_PERIOD_HT);
785 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
786 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
787
788 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
789 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
790 regs + TSADCV2_AUTO_CON);
791 else
792 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
793 regs + TSADCV2_AUTO_CON);
794
795 /*
796 * The general register file will is optional
797 * and might not be available.
798 */
799 if (!IS_ERR(grf)) {
800 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
801 /*
802 * RK3568 TRM, section 18.5. requires a delay no less
803 * than 10us between the rising edge of tsadc_tsen_en
804 * and the rising edge of tsadc_ana_reg_0/1/2.
805 */
806 udelay(15);
807 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
808 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
809 regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
810
811 /*
812 * RK3568 TRM, section 18.5. requires a delay no less
813 * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
814 */
815 usleep_range(100, 200);
816 }
817 }
818
rk_tsadcv8_initialize(struct regmap * grf,void __iomem * regs,enum tshut_polarity tshut_polarity)819 static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
820 enum tshut_polarity tshut_polarity)
821 {
822 writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
823 writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
824 regs + TSADCV3_AUTO_PERIOD_HT);
825 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
826 regs + TSADCV3_HIGHT_INT_DEBOUNCE);
827 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
828 regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
829 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
830 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
831 TSADCV2_AUTO_TSHUT_POLARITY_MASK,
832 regs + TSADCV2_AUTO_CON);
833 else
834 writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
835 regs + TSADCV2_AUTO_CON);
836 }
837
rk_tsadcv2_irq_ack(void __iomem * regs)838 static void rk_tsadcv2_irq_ack(void __iomem *regs)
839 {
840 u32 val;
841
842 val = readl_relaxed(regs + TSADCV2_INT_PD);
843 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
844 }
845
rk_tsadcv3_irq_ack(void __iomem * regs)846 static void rk_tsadcv3_irq_ack(void __iomem *regs)
847 {
848 u32 val;
849
850 val = readl_relaxed(regs + TSADCV2_INT_PD);
851 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
852 }
853
rk_tsadcv4_irq_ack(void __iomem * regs)854 static void rk_tsadcv4_irq_ack(void __iomem *regs)
855 {
856 u32 val;
857
858 val = readl_relaxed(regs + TSADCV3_INT_PD);
859 writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
860 val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
861 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
862 regs + TSADCV3_HSHUT_PD);
863 }
864
rk_tsadcv2_control(void __iomem * regs,bool enable)865 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
866 {
867 u32 val;
868
869 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
870 if (enable)
871 val |= TSADCV2_AUTO_EN;
872 else
873 val &= ~TSADCV2_AUTO_EN;
874
875 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
876 }
877
878 /**
879 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
880 * @regs: the base address of tsadc controller
881 * @enable: boolean flag to enable the controller
882 *
883 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
884 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
885 * adc value if setting this bit to enable.
886 */
rk_tsadcv3_control(void __iomem * regs,bool enable)887 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
888 {
889 u32 val;
890
891 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
892 if (enable)
893 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
894 else
895 val &= ~TSADCV2_AUTO_EN;
896
897 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
898 }
899
rk_tsadcv4_control(void __iomem * regs,bool enable)900 static void rk_tsadcv4_control(void __iomem *regs, bool enable)
901 {
902 u32 val;
903
904 if (enable)
905 val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
906 else
907 val = TSADCV2_AUTO_EN_MASK;
908
909 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
910 }
911
rk_tsadcv2_get_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int * temp)912 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
913 int chn, void __iomem *regs, int *temp)
914 {
915 u32 val;
916
917 val = readl_relaxed(regs + TSADCV2_DATA(chn));
918
919 return rk_tsadcv2_code_to_temp(table, val, temp);
920 }
921
rk_tsadcv4_get_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int * temp)922 static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
923 int chn, void __iomem *regs, int *temp)
924 {
925 u32 val;
926
927 val = readl_relaxed(regs + TSADCV3_DATA(chn));
928
929 return rk_tsadcv2_code_to_temp(table, val, temp);
930 }
931
rk_tsadcv2_alarm_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)932 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
933 int chn, void __iomem *regs, int temp)
934 {
935 u32 alarm_value;
936 u32 int_en, int_clr;
937
938 /*
939 * In some cases, some sensors didn't need the trip points, the
940 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
941 * in the end, ignore this case and disable the high temperature
942 * interrupt.
943 */
944 if (temp == INT_MAX) {
945 int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
946 int_clr &= ~TSADCV2_INT_SRC_EN(chn);
947 writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
948 return 0;
949 }
950
951 /* Make sure the value is valid */
952 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
953 if (alarm_value == table->data_mask)
954 return -ERANGE;
955
956 writel_relaxed(alarm_value & table->data_mask,
957 regs + TSADCV2_COMP_INT(chn));
958
959 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
960 int_en |= TSADCV2_INT_SRC_EN(chn);
961 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
962
963 return 0;
964 }
965
rk_tsadcv3_alarm_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)966 static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
967 int chn, void __iomem *regs, int temp)
968 {
969 u32 alarm_value;
970
971 /*
972 * In some cases, some sensors didn't need the trip points, the
973 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
974 * in the end, ignore this case and disable the high temperature
975 * interrupt.
976 */
977 if (temp == INT_MAX) {
978 writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
979 regs + TSADCV3_HT_INT_EN);
980 return 0;
981 }
982 /* Make sure the value is valid */
983 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
984 if (alarm_value == table->data_mask)
985 return -ERANGE;
986 writel_relaxed(alarm_value & table->data_mask,
987 regs + TSADCV3_COMP_INT(chn));
988 writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
989 regs + TSADCV3_HT_INT_EN);
990 return 0;
991 }
992
rk_tsadcv2_tshut_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)993 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
994 int chn, void __iomem *regs, int temp)
995 {
996 u32 tshut_value, val;
997
998 /* Make sure the value is valid */
999 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1000 if (tshut_value == table->data_mask)
1001 return -ERANGE;
1002
1003 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
1004
1005 /* TSHUT will be valid */
1006 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
1007 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
1008
1009 return 0;
1010 }
1011
rk_tsadcv3_tshut_temp(const struct chip_tsadc_table * table,int chn,void __iomem * regs,int temp)1012 static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
1013 int chn, void __iomem *regs, int temp)
1014 {
1015 u32 tshut_value;
1016
1017 /* Make sure the value is valid */
1018 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
1019 if (tshut_value == table->data_mask)
1020 return -ERANGE;
1021
1022 writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
1023
1024 /* TSHUT will be valid */
1025 writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
1026 regs + TSADCV3_AUTO_SRC_CON);
1027
1028 return 0;
1029 }
1030
rk_tsadcv2_tshut_mode(int chn,void __iomem * regs,enum tshut_mode mode)1031 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
1032 enum tshut_mode mode)
1033 {
1034 u32 val;
1035
1036 val = readl_relaxed(regs + TSADCV2_INT_EN);
1037 if (mode == TSHUT_MODE_GPIO) {
1038 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
1039 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1040 } else {
1041 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
1042 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
1043 }
1044
1045 writel_relaxed(val, regs + TSADCV2_INT_EN);
1046 }
1047
rk_tsadcv3_tshut_mode(int chn,void __iomem * regs,enum tshut_mode mode)1048 static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
1049 enum tshut_mode mode)
1050 {
1051 u32 val_gpio, val_cru;
1052
1053 if (mode == TSHUT_MODE_GPIO) {
1054 val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1055 val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
1056 } else {
1057 val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
1058 val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
1059 }
1060 writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
1061 writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
1062 }
1063
1064 static const struct rockchip_tsadc_chip px30_tsadc_data = {
1065 /* cpu, gpu */
1066 .chn_offset = 0,
1067 .chn_num = 2, /* 2 channels for tsadc */
1068
1069 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1070 .tshut_temp = 95000,
1071
1072 .initialize = rk_tsadcv4_initialize,
1073 .irq_ack = rk_tsadcv3_irq_ack,
1074 .control = rk_tsadcv3_control,
1075 .get_temp = rk_tsadcv2_get_temp,
1076 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1077 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1078 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1079
1080 .table = {
1081 .id = rk3328_code_table,
1082 .length = ARRAY_SIZE(rk3328_code_table),
1083 .data_mask = TSADCV2_DATA_MASK,
1084 .mode = ADC_INCREMENT,
1085 },
1086 };
1087
1088 static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
1089 /* cpu */
1090 .chn_offset = 0,
1091 .chn_num = 1, /* one channel for tsadc */
1092
1093 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1094 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1095 .tshut_temp = 95000,
1096
1097 .initialize = rk_tsadcv2_initialize,
1098 .irq_ack = rk_tsadcv3_irq_ack,
1099 .control = rk_tsadcv3_control,
1100 .get_temp = rk_tsadcv2_get_temp,
1101 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1102 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1103 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1104
1105 .table = {
1106 .id = rv1108_table,
1107 .length = ARRAY_SIZE(rv1108_table),
1108 .data_mask = TSADCV2_DATA_MASK,
1109 .mode = ADC_INCREMENT,
1110 },
1111 };
1112
1113 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
1114 /* cpu */
1115 .chn_offset = 0,
1116 .chn_num = 1, /* one channel for tsadc */
1117
1118 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1119 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1120 .tshut_temp = 95000,
1121
1122 .initialize = rk_tsadcv2_initialize,
1123 .irq_ack = rk_tsadcv3_irq_ack,
1124 .control = rk_tsadcv3_control,
1125 .get_temp = rk_tsadcv2_get_temp,
1126 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1127 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1128 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1129
1130 .table = {
1131 .id = rk3228_code_table,
1132 .length = ARRAY_SIZE(rk3228_code_table),
1133 .data_mask = TSADCV3_DATA_MASK,
1134 .mode = ADC_INCREMENT,
1135 },
1136 };
1137
1138 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1139 /* cpu, gpu */
1140 .chn_offset = 1,
1141 .chn_num = 2, /* two channels for tsadc */
1142
1143 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1144 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1145 .tshut_temp = 95000,
1146
1147 .initialize = rk_tsadcv2_initialize,
1148 .irq_ack = rk_tsadcv2_irq_ack,
1149 .control = rk_tsadcv2_control,
1150 .get_temp = rk_tsadcv2_get_temp,
1151 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1152 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1153 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1154
1155 .table = {
1156 .id = rk3288_code_table,
1157 .length = ARRAY_SIZE(rk3288_code_table),
1158 .data_mask = TSADCV2_DATA_MASK,
1159 .mode = ADC_DECREMENT,
1160 },
1161 };
1162
1163 static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1164 /* cpu */
1165 .chn_offset = 0,
1166 .chn_num = 1, /* one channels for tsadc */
1167
1168 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1169 .tshut_temp = 95000,
1170
1171 .initialize = rk_tsadcv2_initialize,
1172 .irq_ack = rk_tsadcv3_irq_ack,
1173 .control = rk_tsadcv3_control,
1174 .get_temp = rk_tsadcv2_get_temp,
1175 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1176 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1177 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1178
1179 .table = {
1180 .id = rk3328_code_table,
1181 .length = ARRAY_SIZE(rk3328_code_table),
1182 .data_mask = TSADCV2_DATA_MASK,
1183 .mode = ADC_INCREMENT,
1184 },
1185 };
1186
1187 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1188 /* cpu, gpu */
1189 .chn_offset = 0,
1190 .chn_num = 2, /* two channels for tsadc */
1191
1192 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1193 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1194 .tshut_temp = 95000,
1195
1196 .initialize = rk_tsadcv3_initialize,
1197 .irq_ack = rk_tsadcv3_irq_ack,
1198 .control = rk_tsadcv3_control,
1199 .get_temp = rk_tsadcv2_get_temp,
1200 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1201 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1202 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1203
1204 .table = {
1205 .id = rk3228_code_table,
1206 .length = ARRAY_SIZE(rk3228_code_table),
1207 .data_mask = TSADCV3_DATA_MASK,
1208 .mode = ADC_INCREMENT,
1209 },
1210 };
1211
1212 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1213 /* cpu, gpu */
1214 .chn_offset = 0,
1215 .chn_num = 2, /* two channels for tsadc */
1216
1217 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1218 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1219 .tshut_temp = 95000,
1220
1221 .initialize = rk_tsadcv2_initialize,
1222 .irq_ack = rk_tsadcv2_irq_ack,
1223 .control = rk_tsadcv2_control,
1224 .get_temp = rk_tsadcv2_get_temp,
1225 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1226 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1227 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1228
1229 .table = {
1230 .id = rk3368_code_table,
1231 .length = ARRAY_SIZE(rk3368_code_table),
1232 .data_mask = TSADCV3_DATA_MASK,
1233 .mode = ADC_INCREMENT,
1234 },
1235 };
1236
1237 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1238 /* cpu, gpu */
1239 .chn_offset = 0,
1240 .chn_num = 2, /* two channels for tsadc */
1241
1242 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1243 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1244 .tshut_temp = 95000,
1245
1246 .initialize = rk_tsadcv3_initialize,
1247 .irq_ack = rk_tsadcv3_irq_ack,
1248 .control = rk_tsadcv3_control,
1249 .get_temp = rk_tsadcv2_get_temp,
1250 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1251 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1252 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1253
1254 .table = {
1255 .id = rk3399_code_table,
1256 .length = ARRAY_SIZE(rk3399_code_table),
1257 .data_mask = TSADCV3_DATA_MASK,
1258 .mode = ADC_INCREMENT,
1259 },
1260 };
1261
1262 static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1263 /* cpu, gpu */
1264 .chn_offset = 0,
1265 .chn_num = 2, /* two channels for tsadc */
1266
1267 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1268 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1269 .tshut_temp = 95000,
1270
1271 .initialize = rk_tsadcv7_initialize,
1272 .irq_ack = rk_tsadcv3_irq_ack,
1273 .control = rk_tsadcv3_control,
1274 .get_temp = rk_tsadcv2_get_temp,
1275 .set_alarm_temp = rk_tsadcv2_alarm_temp,
1276 .set_tshut_temp = rk_tsadcv2_tshut_temp,
1277 .set_tshut_mode = rk_tsadcv2_tshut_mode,
1278
1279 .table = {
1280 .id = rk3568_code_table,
1281 .length = ARRAY_SIZE(rk3568_code_table),
1282 .data_mask = TSADCV2_DATA_MASK,
1283 .mode = ADC_INCREMENT,
1284 },
1285 };
1286
1287 static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
1288 /* top, big_core0, big_core1, little_core, center, gpu, npu */
1289 .chn_offset = 0,
1290 .chn_num = 7, /* seven channels for tsadc */
1291 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1292 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1293 .tshut_temp = 95000,
1294 .initialize = rk_tsadcv8_initialize,
1295 .irq_ack = rk_tsadcv4_irq_ack,
1296 .control = rk_tsadcv4_control,
1297 .get_temp = rk_tsadcv4_get_temp,
1298 .set_alarm_temp = rk_tsadcv3_alarm_temp,
1299 .set_tshut_temp = rk_tsadcv3_tshut_temp,
1300 .set_tshut_mode = rk_tsadcv3_tshut_mode,
1301 .table = {
1302 .id = rk3588_code_table,
1303 .length = ARRAY_SIZE(rk3588_code_table),
1304 .data_mask = TSADCV4_DATA_MASK,
1305 .mode = ADC_INCREMENT,
1306 },
1307 };
1308
1309 static const struct of_device_id of_rockchip_thermal_match[] = {
1310 { .compatible = "rockchip,px30-tsadc",
1311 .data = (void *)&px30_tsadc_data,
1312 },
1313 {
1314 .compatible = "rockchip,rv1108-tsadc",
1315 .data = (void *)&rv1108_tsadc_data,
1316 },
1317 {
1318 .compatible = "rockchip,rk3228-tsadc",
1319 .data = (void *)&rk3228_tsadc_data,
1320 },
1321 {
1322 .compatible = "rockchip,rk3288-tsadc",
1323 .data = (void *)&rk3288_tsadc_data,
1324 },
1325 {
1326 .compatible = "rockchip,rk3328-tsadc",
1327 .data = (void *)&rk3328_tsadc_data,
1328 },
1329 {
1330 .compatible = "rockchip,rk3366-tsadc",
1331 .data = (void *)&rk3366_tsadc_data,
1332 },
1333 {
1334 .compatible = "rockchip,rk3368-tsadc",
1335 .data = (void *)&rk3368_tsadc_data,
1336 },
1337 {
1338 .compatible = "rockchip,rk3399-tsadc",
1339 .data = (void *)&rk3399_tsadc_data,
1340 },
1341 {
1342 .compatible = "rockchip,rk3568-tsadc",
1343 .data = (void *)&rk3568_tsadc_data,
1344 },
1345 {
1346 .compatible = "rockchip,rk3588-tsadc",
1347 .data = (void *)&rk3588_tsadc_data,
1348 },
1349 { /* end */ },
1350 };
1351 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1352
1353 static void
rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor * sensor,bool on)1354 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1355 {
1356 struct thermal_zone_device *tzd = sensor->tzd;
1357
1358 if (on)
1359 thermal_zone_device_enable(tzd);
1360 else
1361 thermal_zone_device_disable(tzd);
1362 }
1363
rockchip_thermal_alarm_irq_thread(int irq,void * dev)1364 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1365 {
1366 struct rockchip_thermal_data *thermal = dev;
1367 int i;
1368
1369 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1370
1371 thermal->chip->irq_ack(thermal->regs);
1372
1373 for (i = 0; i < thermal->chip->chn_num; i++)
1374 thermal_zone_device_update(thermal->sensors[i].tzd,
1375 THERMAL_EVENT_UNSPECIFIED);
1376
1377 return IRQ_HANDLED;
1378 }
1379
rockchip_thermal_set_trips(struct thermal_zone_device * tz,int low,int high)1380 static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, int high)
1381 {
1382 struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
1383 struct rockchip_thermal_data *thermal = sensor->thermal;
1384 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1385
1386 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1387 __func__, sensor->id, low, high);
1388
1389 return tsadc->set_alarm_temp(&tsadc->table,
1390 sensor->id, thermal->regs, high);
1391 }
1392
rockchip_thermal_get_temp(struct thermal_zone_device * tz,int * out_temp)1393 static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp)
1394 {
1395 struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz);
1396 struct rockchip_thermal_data *thermal = sensor->thermal;
1397 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1398 int retval;
1399
1400 retval = tsadc->get_temp(&tsadc->table,
1401 sensor->id, thermal->regs, out_temp);
1402 return retval;
1403 }
1404
1405 static const struct thermal_zone_device_ops rockchip_of_thermal_ops = {
1406 .get_temp = rockchip_thermal_get_temp,
1407 .set_trips = rockchip_thermal_set_trips,
1408 };
1409
rockchip_configure_from_dt(struct device * dev,struct device_node * np,struct rockchip_thermal_data * thermal)1410 static int rockchip_configure_from_dt(struct device *dev,
1411 struct device_node *np,
1412 struct rockchip_thermal_data *thermal)
1413 {
1414 u32 shut_temp, tshut_mode, tshut_polarity;
1415
1416 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1417 dev_warn(dev,
1418 "Missing tshut temp property, using default %d\n",
1419 thermal->chip->tshut_temp);
1420 thermal->tshut_temp = thermal->chip->tshut_temp;
1421 } else {
1422 if (shut_temp > INT_MAX) {
1423 dev_err(dev, "Invalid tshut temperature specified: %d\n",
1424 shut_temp);
1425 return -ERANGE;
1426 }
1427 thermal->tshut_temp = shut_temp;
1428 }
1429
1430 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1431 dev_warn(dev,
1432 "Missing tshut mode property, using default (%s)\n",
1433 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1434 "gpio" : "cru");
1435 thermal->tshut_mode = thermal->chip->tshut_mode;
1436 } else {
1437 thermal->tshut_mode = tshut_mode;
1438 }
1439
1440 if (thermal->tshut_mode > 1) {
1441 dev_err(dev, "Invalid tshut mode specified: %d\n",
1442 thermal->tshut_mode);
1443 return -EINVAL;
1444 }
1445
1446 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1447 &tshut_polarity)) {
1448 dev_warn(dev,
1449 "Missing tshut-polarity property, using default (%s)\n",
1450 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1451 "low" : "high");
1452 thermal->tshut_polarity = thermal->chip->tshut_polarity;
1453 } else {
1454 thermal->tshut_polarity = tshut_polarity;
1455 }
1456
1457 if (thermal->tshut_polarity > 1) {
1458 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1459 thermal->tshut_polarity);
1460 return -EINVAL;
1461 }
1462
1463 /* The tsadc wont to handle the error in here since some SoCs didn't
1464 * need this property.
1465 */
1466 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1467 if (IS_ERR(thermal->grf))
1468 dev_warn(dev, "Missing rockchip,grf property\n");
1469
1470 return 0;
1471 }
1472
1473 static int
rockchip_thermal_register_sensor(struct platform_device * pdev,struct rockchip_thermal_data * thermal,struct rockchip_thermal_sensor * sensor,int id)1474 rockchip_thermal_register_sensor(struct platform_device *pdev,
1475 struct rockchip_thermal_data *thermal,
1476 struct rockchip_thermal_sensor *sensor,
1477 int id)
1478 {
1479 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1480 int error;
1481
1482 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1483
1484 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1485 thermal->tshut_temp);
1486 if (error)
1487 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1488 __func__, thermal->tshut_temp, error);
1489
1490 sensor->thermal = thermal;
1491 sensor->id = id;
1492 sensor->tzd = devm_thermal_of_zone_register(&pdev->dev, id, sensor,
1493 &rockchip_of_thermal_ops);
1494 if (IS_ERR(sensor->tzd)) {
1495 error = PTR_ERR(sensor->tzd);
1496 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1497 id, error);
1498 return error;
1499 }
1500
1501 return 0;
1502 }
1503
1504 /**
1505 * rockchip_thermal_reset_controller - Reset TSADC Controller, reset all tsadc registers.
1506 * @reset: the reset controller of tsadc
1507 */
rockchip_thermal_reset_controller(struct reset_control * reset)1508 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1509 {
1510 reset_control_assert(reset);
1511 usleep_range(10, 20);
1512 reset_control_deassert(reset);
1513 }
1514
rockchip_thermal_probe(struct platform_device * pdev)1515 static int rockchip_thermal_probe(struct platform_device *pdev)
1516 {
1517 struct device_node *np = pdev->dev.of_node;
1518 struct rockchip_thermal_data *thermal;
1519 int irq;
1520 int i;
1521 int error;
1522
1523 irq = platform_get_irq(pdev, 0);
1524 if (irq < 0)
1525 return -EINVAL;
1526
1527 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1528 GFP_KERNEL);
1529 if (!thermal)
1530 return -ENOMEM;
1531
1532 thermal->pdev = pdev;
1533
1534 thermal->chip = device_get_match_data(&pdev->dev);
1535 if (!thermal->chip)
1536 return -EINVAL;
1537
1538 thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num,
1539 sizeof(*thermal->sensors), GFP_KERNEL);
1540 if (!thermal->sensors)
1541 return -ENOMEM;
1542
1543 thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1544 if (IS_ERR(thermal->regs))
1545 return PTR_ERR(thermal->regs);
1546
1547 thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
1548 if (IS_ERR(thermal->reset))
1549 return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
1550 "failed to get tsadc reset.\n");
1551
1552 thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
1553 if (IS_ERR(thermal->clk))
1554 return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
1555 "failed to get tsadc clock.\n");
1556
1557 thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
1558 if (IS_ERR(thermal->pclk))
1559 return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
1560 "failed to get apb_pclk clock.\n");
1561
1562 rockchip_thermal_reset_controller(thermal->reset);
1563
1564 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1565 if (error)
1566 return dev_err_probe(&pdev->dev, error,
1567 "failed to parse device tree data\n");
1568
1569 thermal->chip->initialize(thermal->grf, thermal->regs,
1570 thermal->tshut_polarity);
1571
1572 for (i = 0; i < thermal->chip->chn_num; i++) {
1573 error = rockchip_thermal_register_sensor(pdev, thermal,
1574 &thermal->sensors[i],
1575 thermal->chip->chn_offset + i);
1576 if (error)
1577 return dev_err_probe(&pdev->dev, error,
1578 "failed to register sensor[%d].\n", i);
1579 }
1580
1581 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1582 &rockchip_thermal_alarm_irq_thread,
1583 IRQF_ONESHOT,
1584 "rockchip_thermal", thermal);
1585 if (error)
1586 return dev_err_probe(&pdev->dev, error,
1587 "failed to request tsadc irq.\n");
1588
1589 thermal->chip->control(thermal->regs, true);
1590
1591 for (i = 0; i < thermal->chip->chn_num; i++) {
1592 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1593 error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1594 if (error)
1595 dev_warn(&pdev->dev,
1596 "failed to register sensor %d with hwmon: %d\n",
1597 i, error);
1598 }
1599
1600 platform_set_drvdata(pdev, thermal);
1601
1602 return 0;
1603 }
1604
rockchip_thermal_remove(struct platform_device * pdev)1605 static void rockchip_thermal_remove(struct platform_device *pdev)
1606 {
1607 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1608 int i;
1609
1610 for (i = 0; i < thermal->chip->chn_num; i++) {
1611 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1612
1613 thermal_remove_hwmon_sysfs(sensor->tzd);
1614 rockchip_thermal_toggle_sensor(sensor, false);
1615 }
1616
1617 thermal->chip->control(thermal->regs, false);
1618 }
1619
rockchip_thermal_suspend(struct device * dev)1620 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1621 {
1622 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1623 int i;
1624
1625 for (i = 0; i < thermal->chip->chn_num; i++)
1626 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1627
1628 thermal->chip->control(thermal->regs, false);
1629
1630 clk_disable(thermal->pclk);
1631 clk_disable(thermal->clk);
1632
1633 pinctrl_pm_select_sleep_state(dev);
1634
1635 return 0;
1636 }
1637
rockchip_thermal_resume(struct device * dev)1638 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1639 {
1640 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1641 int i;
1642 int error;
1643
1644 error = clk_enable(thermal->clk);
1645 if (error)
1646 return error;
1647
1648 error = clk_enable(thermal->pclk);
1649 if (error) {
1650 clk_disable(thermal->clk);
1651 return error;
1652 }
1653
1654 rockchip_thermal_reset_controller(thermal->reset);
1655
1656 thermal->chip->initialize(thermal->grf, thermal->regs,
1657 thermal->tshut_polarity);
1658
1659 for (i = 0; i < thermal->chip->chn_num; i++) {
1660 int id = thermal->sensors[i].id;
1661
1662 thermal->chip->set_tshut_mode(id, thermal->regs,
1663 thermal->tshut_mode);
1664
1665 error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1666 id, thermal->regs,
1667 thermal->tshut_temp);
1668 if (error)
1669 dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1670 __func__, thermal->tshut_temp, error);
1671 }
1672
1673 thermal->chip->control(thermal->regs, true);
1674
1675 for (i = 0; i < thermal->chip->chn_num; i++)
1676 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1677
1678 pinctrl_pm_select_default_state(dev);
1679
1680 return 0;
1681 }
1682
1683 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1684 rockchip_thermal_suspend, rockchip_thermal_resume);
1685
1686 static struct platform_driver rockchip_thermal_driver = {
1687 .driver = {
1688 .name = "rockchip-thermal",
1689 .pm = &rockchip_thermal_pm_ops,
1690 .of_match_table = of_rockchip_thermal_match,
1691 },
1692 .probe = rockchip_thermal_probe,
1693 .remove = rockchip_thermal_remove,
1694 };
1695
1696 module_platform_driver(rockchip_thermal_driver);
1697
1698 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1699 MODULE_AUTHOR("Rockchip, Inc.");
1700 MODULE_LICENSE("GPL v2");
1701 MODULE_ALIAS("platform:rockchip-thermal");
1702