1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 enum ftr_type {
19 FTR_EXACT, /* Use a predefined safe value */
20 FTR_LOWER_SAFE, /* Smaller value is safe */
21 FTR_HIGHER_SAFE, /* Bigger value is safe */
22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
23 FTR_END, /* Mark the last ftr bits */
24 };
25
26 #define FTR_SIGNED true /* Value should be treated as signed */
27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
28
29 struct reg_ftr_bits {
30 char *name;
31 bool sign;
32 enum ftr_type type;
33 uint8_t shift;
34 uint64_t mask;
35 /*
36 * For FTR_EXACT, safe_val is used as the exact safe value.
37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
38 */
39 int64_t safe_val;
40 };
41
42 struct test_feature_reg {
43 uint32_t reg;
44 const struct reg_ftr_bits *ftr_bits;
45 };
46
47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
48 { \
49 .name = #NAME, \
50 .sign = SIGNED, \
51 .type = TYPE, \
52 .shift = SHIFT, \
53 .mask = MASK, \
54 .safe_val = SAFE_VAL, \
55 }
56
57 #define REG_FTR_BITS(type, reg, field, safe_val) \
58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
59 reg##_##field##_MASK, safe_val)
60
61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
63 reg##_##field##_MASK, safe_val)
64
65 #define REG_FTR_END \
66 { \
67 .type = FTR_END, \
68 }
69
70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
75 REG_FTR_END,
76 };
77
78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
81 REG_FTR_END,
82 };
83
84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
100 REG_FTR_END,
101 };
102
103 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
116 REG_FTR_END,
117 };
118
119 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
123 REG_FTR_END,
124 };
125
126 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
130 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
131 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
132 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 0),
133 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 0),
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 0),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 0),
136 REG_FTR_END,
137 };
138
139 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
143 REG_FTR_END,
144 };
145
146 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
149 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
150 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
151 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
152 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
153 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
154 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
156 REG_FTR_END,
157 };
158
159 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
160 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
161 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
163 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
167 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
168 REG_FTR_END,
169 };
170
171 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
176 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
181 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
182 REG_FTR_END,
183 };
184
185 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
188 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
195 REG_FTR_END,
196 };
197
198 #define TEST_REG(id, table) \
199 { \
200 .reg = id, \
201 .ftr_bits = &((table)[0]), \
202 }
203
204 static struct test_feature_reg test_regs[] = {
205 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
206 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
207 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
208 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
209 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
210 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
211 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
212 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
213 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
214 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
215 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
216 };
217
218 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
219
guest_code(void)220 static void guest_code(void)
221 {
222 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
223 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
224 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
225 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
226 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
227 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
228 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
229 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
230 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
231 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
232 GUEST_REG_SYNC(SYS_CTR_EL0);
233
234 GUEST_DONE();
235 }
236
237 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)238 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
239 {
240 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
241
242 if (ftr_bits->sign == FTR_UNSIGNED) {
243 switch (ftr_bits->type) {
244 case FTR_EXACT:
245 ftr = ftr_bits->safe_val;
246 break;
247 case FTR_LOWER_SAFE:
248 if (ftr > ftr_bits->safe_val)
249 ftr--;
250 break;
251 case FTR_HIGHER_SAFE:
252 if (ftr < ftr_max)
253 ftr++;
254 break;
255 case FTR_HIGHER_OR_ZERO_SAFE:
256 if (ftr == ftr_max)
257 ftr = 0;
258 else if (ftr != 0)
259 ftr++;
260 break;
261 default:
262 break;
263 }
264 } else if (ftr != ftr_max) {
265 switch (ftr_bits->type) {
266 case FTR_EXACT:
267 ftr = ftr_bits->safe_val;
268 break;
269 case FTR_LOWER_SAFE:
270 if (ftr > ftr_bits->safe_val)
271 ftr--;
272 break;
273 case FTR_HIGHER_SAFE:
274 if (ftr < ftr_max - 1)
275 ftr++;
276 break;
277 case FTR_HIGHER_OR_ZERO_SAFE:
278 if (ftr != 0 && ftr != ftr_max - 1)
279 ftr++;
280 break;
281 default:
282 break;
283 }
284 }
285
286 return ftr;
287 }
288
289 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)290 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
291 {
292 uint64_t ftr_max = GENMASK_ULL(ARM64_FEATURE_FIELD_BITS - 1, 0);
293
294 if (ftr_bits->sign == FTR_UNSIGNED) {
295 switch (ftr_bits->type) {
296 case FTR_EXACT:
297 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
298 break;
299 case FTR_LOWER_SAFE:
300 ftr++;
301 break;
302 case FTR_HIGHER_SAFE:
303 ftr--;
304 break;
305 case FTR_HIGHER_OR_ZERO_SAFE:
306 if (ftr == 0)
307 ftr = ftr_max;
308 else
309 ftr--;
310 break;
311 default:
312 break;
313 }
314 } else if (ftr != ftr_max) {
315 switch (ftr_bits->type) {
316 case FTR_EXACT:
317 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
318 break;
319 case FTR_LOWER_SAFE:
320 ftr++;
321 break;
322 case FTR_HIGHER_SAFE:
323 ftr--;
324 break;
325 case FTR_HIGHER_OR_ZERO_SAFE:
326 if (ftr == 0)
327 ftr = ftr_max - 1;
328 else
329 ftr--;
330 break;
331 default:
332 break;
333 }
334 } else {
335 ftr = 0;
336 }
337
338 return ftr;
339 }
340
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)341 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
342 const struct reg_ftr_bits *ftr_bits)
343 {
344 uint8_t shift = ftr_bits->shift;
345 uint64_t mask = ftr_bits->mask;
346 uint64_t val, new_val, ftr;
347
348 val = vcpu_get_reg(vcpu, reg);
349 ftr = (val & mask) >> shift;
350
351 ftr = get_safe_value(ftr_bits, ftr);
352
353 ftr <<= shift;
354 val &= ~mask;
355 val |= ftr;
356
357 vcpu_set_reg(vcpu, reg, val);
358 new_val = vcpu_get_reg(vcpu, reg);
359 TEST_ASSERT_EQ(new_val, val);
360
361 return new_val;
362 }
363
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)364 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
365 const struct reg_ftr_bits *ftr_bits)
366 {
367 uint8_t shift = ftr_bits->shift;
368 uint64_t mask = ftr_bits->mask;
369 uint64_t val, old_val, ftr;
370 int r;
371
372 val = vcpu_get_reg(vcpu, reg);
373 ftr = (val & mask) >> shift;
374
375 ftr = get_invalid_value(ftr_bits, ftr);
376
377 old_val = val;
378 ftr <<= shift;
379 val &= ~mask;
380 val |= ftr;
381
382 r = __vcpu_set_reg(vcpu, reg, val);
383 TEST_ASSERT(r < 0 && errno == EINVAL,
384 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
385
386 val = vcpu_get_reg(vcpu, reg);
387 TEST_ASSERT_EQ(val, old_val);
388 }
389
390 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
391
392 #define encoding_to_range_idx(encoding) \
393 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
394 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
395 sys_reg_Op2(encoding))
396
397
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)398 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
399 {
400 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
401 struct reg_mask_range range = {
402 .addr = (__u64)masks,
403 };
404 int ret;
405
406 /* KVM should return error when reserved field is not zero */
407 range.reserved[0] = 1;
408 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
409 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
410
411 /* Get writable masks for feature ID registers */
412 memset(range.reserved, 0, sizeof(range.reserved));
413 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
414
415 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
416 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
417 uint32_t reg_id = test_regs[i].reg;
418 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
419 int idx;
420
421 /* Get the index to masks array for the idreg */
422 idx = encoding_to_range_idx(reg_id);
423
424 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
425 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
426 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
427 ksft_test_result_skip("%s on AARCH64 only system\n",
428 ftr_bits[j].name);
429 continue;
430 }
431
432 /* Make sure the feature field is writable */
433 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
434
435 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
436
437 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
438 &ftr_bits[j]);
439
440 ksft_test_result_pass("%s\n", ftr_bits[j].name);
441 }
442 }
443 }
444
445 #define MPAM_IDREG_TEST 6
test_user_set_mpam_reg(struct kvm_vcpu * vcpu)446 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
447 {
448 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
449 struct reg_mask_range range = {
450 .addr = (__u64)masks,
451 };
452 uint64_t val;
453 int idx, err;
454
455 /*
456 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero,
457 * check that if it can be set to 1, (i.e. it is supported by the
458 * hardware), that it can't be set to other values.
459 */
460
461 /* Get writable masks for feature ID registers */
462 memset(range.reserved, 0, sizeof(range.reserved));
463 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
464
465 /* Writeable? Nothing to test! */
466 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1);
467 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) {
468 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n");
469 return;
470 }
471
472 /* Get the id register value */
473 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
474
475 /* Try to set MPAM=0. This should always be possible. */
476 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
477 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0);
478 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
479 if (err)
480 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n");
481 else
482 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n");
483
484 /* Try to set MPAM=1 */
485 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
486 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1);
487 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
488 if (err)
489 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n");
490 else
491 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n");
492
493 /* Try to set MPAM=2 */
494 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
495 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2);
496 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
497 if (err)
498 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n");
499 else
500 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n");
501
502 /* And again for ID_AA64PFR1_EL1.MPAM_frac */
503 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
504 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) {
505 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n");
506 return;
507 }
508
509 /* Get the id register value */
510 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
511
512 /* Try to set MPAM_frac=0. This should always be possible. */
513 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
514 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0);
515 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
516 if (err)
517 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n");
518 else
519 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n");
520
521 /* Try to set MPAM_frac=1 */
522 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
523 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1);
524 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
525 if (err)
526 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n");
527 else
528 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n");
529
530 /* Try to set MPAM_frac=2 */
531 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
532 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2);
533 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
534 if (err)
535 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n");
536 else
537 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n");
538 }
539
test_guest_reg_read(struct kvm_vcpu * vcpu)540 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
541 {
542 bool done = false;
543 struct ucall uc;
544
545 while (!done) {
546 vcpu_run(vcpu);
547
548 switch (get_ucall(vcpu, &uc)) {
549 case UCALL_ABORT:
550 REPORT_GUEST_ASSERT(uc);
551 break;
552 case UCALL_SYNC:
553 /* Make sure the written values are seen by guest */
554 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
555 uc.args[3]);
556 break;
557 case UCALL_DONE:
558 done = true;
559 break;
560 default:
561 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
562 }
563 }
564 }
565
566 /* Politely lifted from arch/arm64/include/asm/cache.h */
567 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
568 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
569 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
570 #define CLIDR_CTYPE(clidr, level) \
571 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
572
test_clidr(struct kvm_vcpu * vcpu)573 static void test_clidr(struct kvm_vcpu *vcpu)
574 {
575 uint64_t clidr;
576 int level;
577
578 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
579
580 /* find the first empty level in the cache hierarchy */
581 for (level = 1; level < 7; level++) {
582 if (!CLIDR_CTYPE(clidr, level))
583 break;
584 }
585
586 /*
587 * If you have a mind-boggling 7 levels of cache, congratulations, you
588 * get to fix this.
589 */
590 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
591
592 /* stick in a unified cache level */
593 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
594
595 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
596 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
597 }
598
test_ctr(struct kvm_vcpu * vcpu)599 static void test_ctr(struct kvm_vcpu *vcpu)
600 {
601 u64 ctr;
602
603 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
604 ctr &= ~CTR_EL0_DIC_MASK;
605 if (ctr & CTR_EL0_IminLine_MASK)
606 ctr--;
607
608 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
609 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
610 }
611
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)612 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
613 {
614 u64 val;
615
616 test_clidr(vcpu);
617 test_ctr(vcpu);
618
619 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1));
620 val++;
621 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), val);
622
623 test_reg_vals[encoding_to_range_idx(SYS_MPIDR_EL1)] = val;
624 ksft_test_result_pass("%s\n", __func__);
625 }
626
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)627 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
628 {
629 size_t idx = encoding_to_range_idx(encoding);
630 uint64_t observed;
631
632 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
633 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
634 }
635
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)636 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
637 {
638 /*
639 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
640 * architectural reset of the vCPU.
641 */
642 aarch64_vcpu_setup(vcpu, NULL);
643
644 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
645 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
646
647 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
648 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
649 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
650
651 ksft_test_result_pass("%s\n", __func__);
652 }
653
main(void)654 int main(void)
655 {
656 struct kvm_vcpu *vcpu;
657 struct kvm_vm *vm;
658 bool aarch64_only;
659 uint64_t val, el0;
660 int test_cnt;
661
662 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
663
664 vm = vm_create_with_one_vcpu(&vcpu, guest_code);
665
666 /* Check for AARCH64 only system */
667 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
668 el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
669 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
670
671 ksft_print_header();
672
673 test_cnt = ARRAY_SIZE(ftr_id_aa64dfr0_el1) + ARRAY_SIZE(ftr_id_dfr0_el1) +
674 ARRAY_SIZE(ftr_id_aa64isar0_el1) + ARRAY_SIZE(ftr_id_aa64isar1_el1) +
675 ARRAY_SIZE(ftr_id_aa64isar2_el1) + ARRAY_SIZE(ftr_id_aa64pfr0_el1) +
676 ARRAY_SIZE(ftr_id_aa64pfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr0_el1) +
677 ARRAY_SIZE(ftr_id_aa64mmfr1_el1) + ARRAY_SIZE(ftr_id_aa64mmfr2_el1) +
678 ARRAY_SIZE(ftr_id_aa64zfr0_el1) - ARRAY_SIZE(test_regs) + 2 +
679 MPAM_IDREG_TEST;
680
681 ksft_set_plan(test_cnt);
682
683 test_vm_ftr_id_regs(vcpu, aarch64_only);
684 test_vcpu_ftr_id_regs(vcpu);
685 test_user_set_mpam_reg(vcpu);
686
687 test_guest_reg_read(vcpu);
688
689 test_reset_preserves_id_regs(vcpu);
690
691 kvm_vm_free(vm);
692
693 ksft_finished();
694 }
695