AXI4Timer.scala (f320e0f01bd645f0a3045a8a740e60dd770734a9) AXI4Timer.scala (3c02ee8f82edea481fa8336c7f54ffc17fafba91)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chipsalliance.rocketchip.config.Parameters
21import freechips.rocketchip.diplomacy.AddressSet
22import utils._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 6 unchanged lines hidden (view full) ---

15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chipsalliance.rocketchip.config.Parameters
21import freechips.rocketchip.diplomacy.AddressSet
22import utils._
23import utility._
23
24class TimerIO extends Bundle {
25 val mtip = Output(Bool())
26}
27
28class AXI4Timer
29(
30 sim: Boolean = false,

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25class TimerIO extends Bundle {
26 val mtip = Output(Bool())
27}
28
29class AXI4Timer
30(
31 sim: Boolean = false,

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