xref: /XiangShan/src/main/scala/device/AXI4Timer.scala (revision 8891a219bbc84f568e1d134854d8d5ed86d6d560) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import org.chipsalliance.cde.config.Parameters
21import freechips.rocketchip.diplomacy.AddressSet
22import utils._
23import utility._
24
25class TimerIO extends Bundle {
26  val mtip = Output(Bool())
27}
28
29class AXI4Timer
30(
31  sim: Boolean = false,
32  address: Seq[AddressSet]
33)(implicit p: Parameters)
34  extends AXI4SlaveModule(address, executable = false, _extra = new TimerIO)
35{
36  override lazy val module = new AXI4SlaveModuleImp[TimerIO](this){
37    val mtime = RegInit(0.U(64.W))  // unit: us
38    val mtimecmp = RegInit(0.U(64.W))
39
40    val clk = (if (!sim) 40 /* 40MHz / 1000000 */ else 10000)
41    val freq = RegInit(clk.U(16.W))
42    val inc = RegInit(1000.U(16.W))
43
44    val cnt = RegInit(0.U(16.W))
45    val nextCnt = cnt + 1.U
46    cnt := Mux(nextCnt < freq, nextCnt, 0.U)
47    val tick = (nextCnt === freq)
48    when (tick) { mtime := mtime + inc }
49
50    val mapping = Map(
51      RegMap(0x4000, mtimecmp),
52      RegMap(0x8000, freq),
53      RegMap(0x8008, inc),
54      RegMap(0xbff8, mtime)
55    )
56    def getOffset(addr: UInt) = addr(15,0)
57
58    RegMap.generate(mapping, getOffset(raddr), in.r.bits.data,
59      getOffset(waddr), in.w.fire, in.w.bits.data, MaskExpand(in.w.bits.strb))
60
61    io.extra.get.mtip := RegNext(mtime >= mtimecmp)
62  }
63}
64