Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G,

AXI4SlaveModule: use Seq[AddressSet] instead of AddressSet
to allow more flexible address range configuration.
With only one AddressSet, we can not even represent
very simple address ranges like [2G, 32G).

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src: remove unused import BoringUtils

AXI4Timer: remove isWFI

Rewrite AXI4Timer, Add AXI4Timer Test

Cache, Timer: fix cache addressSpace bug, increase timer inc

device,AXI4Timer: add programmable freq and inc

* This can help to generate desired frequency of timer interrupt, no
matter what frequency of the clock is.

device,AXI4Timer: advance mtime aggressively when executing wfi

* this can reduce the idle time in Linux

device,AXI4Timer: use us as the unit of mtime

* this match the tick frequency in linux

device,AXI4Timer: make the register offset match standard CLINT

system,SoC: add meip

device,AXI4Timer: latch mtip to fix synchronization

* now vivado reports good timing across clock domains

device,AXI4Timer: support mtime and mtimecmp

fpga,axu3cg: add hdmi support

* change the fix clk to 40MHz to obtain good timing result
* 50MHz and the 27MHz i2c clock yield bad timing result for inter-clock

device: add AXI4Keyboard but not tested, since zedboard does not have PS2 interface

device: add AXI4Slave to refactor code

device: use BoolStopWatch for axi slave

bus,axi4,AXI4RAM: move to device package

device,AXI4Timer: use AXI4-Lite port

bus: re-organize the directory structure

device,AXI4Timer: maintain rvalid and bvalid until the channels are ready