Backend.scala (602aa9f1a8fb63310bea30e8b3e247e5aca5f123) Backend.scala (8cfc24b28454f1915c339ce79485711f8e438f59)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

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21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967.
22***************************************************************************************/
23
24package xiangshan.backend
25
26import org.chipsalliance.cde.config.Parameters
27import chisel3._
28import chisel3.util._
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 12 unchanged lines hidden (view full) ---

21* (https://doi.org/10.1147/rd.111.0025)" IBM Journal of Research and Development (IBMJ) 11.1: 25-33. 1967.
22***************************************************************************************/
23
24package xiangshan.backend
25
26import org.chipsalliance.cde.config.Parameters
27import chisel3._
28import chisel3.util._
29import device.MsiInfoBundle
30import difftest._
31import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
32import system.HasSoCParameter
33import utility._
34import utility.sram.SramMbistBundle
35import xiangshan._
36import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals}
37import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}

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946 XSError(error, s"critical error: $name \n")
947 }
948 }
949
950 // expand to collect frontend/memblock/L2 critical errors
951 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _)
952
953 io.toTop.cpuCriticalError := csrio.criticalErrorState
29import difftest._
30import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
31import system.HasSoCParameter
32import utility._
33import utility.sram.SramMbistBundle
34import xiangshan._
35import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, LoadShouldCancel, MemExuInput, MemExuOutput, VPUCtrlSignals}
36import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo}

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945 XSError(error, s"critical error: $name \n")
946 }
947 }
948
949 // expand to collect frontend/memblock/L2 critical errors
950 backendCriticalError := criticalErrors.map(_._2).reduce(_ || _)
951
952 io.toTop.cpuCriticalError := csrio.criticalErrorState
953 io.toTop.msiAck := csrio.msiAck
954}
955
956class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle {
957 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts
958 val flippedLda = true
959 // params alias
960 private val LoadQueueSize = VirtualLoadQueueSize
961 // In/Out // Todo: split it into one-direction bundle

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1041
1042 // store event difftest information
1043 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
1044 val robidx = Input(new RobPtr)
1045 val pc = Output(UInt(VAddrBits.W))
1046 })
1047}
1048
954}
955
956class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle {
957 // Since fast load replay always use load unit 0, Backend flips two load port to avoid conflicts
958 val flippedLda = true
959 // params alias
960 private val LoadQueueSize = VirtualLoadQueueSize
961 // In/Out // Todo: split it into one-direction bundle

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1041
1042 // store event difftest information
1043 val storeDebugInfo = Vec(EnsbufferWidth, new Bundle {
1044 val robidx = Input(new RobPtr)
1045 val pc = Output(UInt(VAddrBits.W))
1046 })
1047}
1048
1049class TopToBackendBundle(implicit p: Parameters) extends XSBundle {
1049class TopToBackendBundle(implicit p: Parameters) extends XSBundle with HasSoCParameter {
1050 val hartId = Output(UInt(hartIdLen.W))
1051 val externalInterrupt = Output(new ExternalInterruptIO)
1050 val hartId = Output(UInt(hartIdLen.W))
1051 val externalInterrupt = Output(new ExternalInterruptIO)
1052 val msiInfo = Output(ValidIO(new MsiInfoBundle))
1052 val msiInfo = Output(ValidIO(UInt(soc.IMSICParams.MSI_INFO_WIDTH.W)))
1053 val clintTime = Output(ValidIO(UInt(64.W)))
1054 val l2FlushDone = Output(Bool())
1055}
1056
1057class BackendToTopBundle extends Bundle {
1058 val cpuHalted = Output(Bool())
1059 val cpuCriticalError = Output(Bool())
1053 val clintTime = Output(ValidIO(UInt(64.W)))
1054 val l2FlushDone = Output(Bool())
1055}
1056
1057class BackendToTopBundle extends Bundle {
1058 val cpuHalted = Output(Bool())
1059 val cpuCriticalError = Output(Bool())
1060 val msiAck = Output(Bool())
1060}
1061
1062class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter {
1063 val fromTop = Flipped(new TopToBackendBundle)
1064
1065 val toTop = new BackendToTopBundle
1066
1067 val traceCoreInterface = new TraceCoreInterface(hasOffset = true)

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1062
1063class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle with HasSoCParameter {
1064 val fromTop = Flipped(new TopToBackendBundle)
1065
1066 val toTop = new BackendToTopBundle
1067
1068 val traceCoreInterface = new TraceCoreInterface(hasOffset = true)

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