SC.scala (b2564f6cd76e15b14a00c1fbeb2030bdfbb6af57) SC.scala (cf7d6b7a1a781c73aeb87de112de2e7fe5ea3b7c)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend
18
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.frontend
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
19import chisel3._
20import chisel3.util._
22import xiangshan._
23import utils._
21import org.chipsalliance.cde.config.Parameters
22import scala.{Tuple2 => &}
23import scala.math.min
24import utility._
24import utility._
25import utils._
26import xiangshan._
25
27
26import scala.math.min
27import scala.{Tuple2 => &}
28trait HasSCParameter extends TageParams {}
28
29
29trait HasSCParameter extends TageParams {
30}
31
32class SCReq(implicit p: Parameters) extends TageReq
33
34abstract class SCBundle(implicit p: Parameters) extends TageBundle with HasSCParameter {}
35abstract class SCModule(implicit p: Parameters) extends TageModule with HasSCParameter {}
36
30class SCReq(implicit p: Parameters) extends TageReq
31
32abstract class SCBundle(implicit p: Parameters) extends TageBundle with HasSCParameter {}
33abstract class SCModule(implicit p: Parameters) extends TageModule with HasSCParameter {}
34
37
38class SCMeta(val ntables: Int)(implicit p: Parameters) extends XSBundle with HasSCParameter {
39 val scPreds = Vec(numBr, Bool())
40 // Suppose ctrbits of all tables are identical
41 val ctrs = Vec(numBr, Vec(ntables, SInt(SCCtrBits.W)))
42}
43
35class SCMeta(val ntables: Int)(implicit p: Parameters) extends XSBundle with HasSCParameter {
36 val scPreds = Vec(numBr, Bool())
37 // Suppose ctrbits of all tables are identical
38 val ctrs = Vec(numBr, Vec(ntables, SInt(SCCtrBits.W)))
39}
40
44
45class SCResp(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
46 val ctrs = Vec(numBr, Vec(2, SInt(ctrBits.W)))
47}
48
49class SCUpdate(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
41class SCResp(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
42 val ctrs = Vec(numBr, Vec(2, SInt(ctrBits.W)))
43}
44
45class SCUpdate(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
50 val pc = UInt(VAddrBits.W)
51 val ghist = UInt(HistoryLength.W)
52 val mask = Vec(numBr, Bool())
53 val oldCtrs = Vec(numBr, SInt(ctrBits.W))
46 val pc = UInt(VAddrBits.W)
47 val ghist = UInt(HistoryLength.W)
48 val mask = Vec(numBr, Bool())
49 val oldCtrs = Vec(numBr, SInt(ctrBits.W))
54 val tagePreds = Vec(numBr, Bool())
50 val tagePreds = Vec(numBr, Bool())
55 val takens = Vec(numBr, Bool())
51 val takens = Vec(numBr, Bool())
56}
57
58class SCTableIO(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
52}
53
54class SCTableIO(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
59 val req = Input(Valid(new SCReq))
60 val resp = Output(new SCResp(ctrBits))
55 val req = Input(Valid(new SCReq))
56 val resp = Output(new SCResp(ctrBits))
61 val update = Input(new SCUpdate(ctrBits))
62}
63
64class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)(implicit p: Parameters)
57 val update = Input(new SCUpdate(ctrBits))
58}
59
60class SCTable(val nRows: Int, val ctrBits: Int, val histLen: Int)(implicit p: Parameters)
65 extends SCModule with HasFoldedHistory {
61 extends SCModule with HasFoldedHistory {
66 val io = IO(new SCTableIO(ctrBits))
67
68 // val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false))
62 val io = IO(new SCTableIO(ctrBits))
63
64 // val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false))
69 val table = Module(new SRAMTemplate(SInt(ctrBits.W), set=nRows, way=2*TageBanks, shouldReset=true, holdRead=true, singlePort=false, bypassWrite=true))
65 val table = Module(new SRAMTemplate(
66 SInt(ctrBits.W),
67 set = nRows,
68 way = 2 * TageBanks,
69 shouldReset = true,
70 holdRead = true,
71 singlePort = false,
72 bypassWrite = true
73 ))
70
71 // def getIdx(hist: UInt, pc: UInt) = {
72 // (compute_folded_ghist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits))(log2Ceil(nRows)-1,0)
73 // }
74
74
75 // def getIdx(hist: UInt, pc: UInt) = {
76 // (compute_folded_ghist(hist, log2Ceil(nRows)) ^ (pc >> instOffsetBits))(log2Ceil(nRows)-1,0)
77 // }
78
75
76 val idxFhInfo = (histLen, min(log2Ceil(nRows), histLen))
77
78 def getFoldedHistoryInfo = Set(idxFhInfo).filter(_._1 > 0)
79
79 val idxFhInfo = (histLen, min(log2Ceil(nRows), histLen))
80
81 def getFoldedHistoryInfo = Set(idxFhInfo).filter(_._1 > 0)
82
80 def getIdx(pc: UInt, allFh: AllFoldedHistories) = {
83 def getIdx(pc: UInt, allFh: AllFoldedHistories) =
81 if (histLen > 0) {
82 val idx_fh = allFh.getHistWithInfo(idxFhInfo).folded_hist
83 // require(idx_fh.getWidth == log2Ceil(nRows))
84 if (histLen > 0) {
85 val idx_fh = allFh.getHistWithInfo(idxFhInfo).folded_hist
86 // require(idx_fh.getWidth == log2Ceil(nRows))
84 ((pc >> instOffsetBits) ^ idx_fh)(log2Ceil(nRows)-1,0)
87 ((pc >> instOffsetBits) ^ idx_fh)(log2Ceil(nRows) - 1, 0)
88 } else {
89 (pc >> instOffsetBits)(log2Ceil(nRows) - 1, 0)
85 }
90 }
86 else {
87 (pc >> instOffsetBits)(log2Ceil(nRows)-1,0)
88 }
89 }
90
91
91
92 def ctrUpdate(ctr: SInt, cond: Bool): SInt = signedSatUpdate(ctr, ctrBits, cond)
93
94 val s0_idx = getIdx(io.req.bits.pc, io.req.bits.folded_hist)
95 val s1_idx = RegEnable(s0_idx, io.req.valid)
96
92 def ctrUpdate(ctr: SInt, cond: Bool): SInt = signedSatUpdate(ctr, ctrBits, cond)
93
94 val s0_idx = getIdx(io.req.bits.pc, io.req.bits.folded_hist)
95 val s1_idx = RegEnable(s0_idx, io.req.valid)
96
97 val s1_pc = RegEnable(io.req.bits.pc, io.req.fire)
97 val s1_pc = RegEnable(io.req.bits.pc, io.req.fire)
98 val s1_unhashed_idx = s1_pc >> instOffsetBits
99
98 val s1_unhashed_idx = s1_pc >> instOffsetBits
99
100 table.io.r.req.valid := io.req.valid
100 table.io.r.req.valid := io.req.valid
101 table.io.r.req.bits.setIdx := s0_idx
102
101 table.io.r.req.bits.setIdx := s0_idx
102
103 val update_wdata = Wire(Vec(numBr, SInt(ctrBits.W))) // correspond to physical bridx
104 val update_wdata_packed = VecInit(update_wdata.map(Seq.fill(2)(_)).reduce(_++_))
105 val updateWayMask = Wire(Vec(2*numBr, Bool())) // correspond to physical bridx
103 val update_wdata = Wire(Vec(numBr, SInt(ctrBits.W))) // correspond to physical bridx
104 val update_wdata_packed = VecInit(update_wdata.map(Seq.fill(2)(_)).reduce(_ ++ _))
105 val updateWayMask = Wire(Vec(2 * numBr, Bool())) // correspond to physical bridx
106
107 val update_unhashed_idx = io.update.pc >> instOffsetBits
108 for (pi <- 0 until numBr) {
106
107 val update_unhashed_idx = io.update.pc >> instOffsetBits
108 for (pi <- 0 until numBr) {
109 updateWayMask(2*pi) := Seq.tabulate(numBr)(li =>
109 updateWayMask(2 * pi) := Seq.tabulate(numBr)(li =>
110 io.update.mask(li) && get_phy_br_idx(update_unhashed_idx, li) === pi.U && !io.update.tagePreds(li)
110 io.update.mask(li) && get_phy_br_idx(update_unhashed_idx, li) === pi.U && !io.update.tagePreds(li)
111 ).reduce(_||_)
112 updateWayMask(2*pi+1) := Seq.tabulate(numBr)(li =>
113 io.update.mask(li) && get_phy_br_idx(update_unhashed_idx, li) === pi.U && io.update.tagePreds(li)
114 ).reduce(_||_)
111 ).reduce(_ || _)
112 updateWayMask(2 * pi + 1) := Seq.tabulate(numBr)(li =>
113 io.update.mask(li) && get_phy_br_idx(update_unhashed_idx, li) === pi.U && io.update.tagePreds(li)
114 ).reduce(_ || _)
115 }
116
117 val update_folded_hist = WireInit(0.U.asTypeOf(new AllFoldedHistories(foldedGHistInfos)))
118 if (histLen > 0) {
119 update_folded_hist.getHistWithInfo(idxFhInfo).folded_hist := compute_folded_ghist(io.update.ghist, log2Ceil(nRows))
120 }
121 val update_idx = getIdx(io.update.pc, update_folded_hist)
122
115 }
116
117 val update_folded_hist = WireInit(0.U.asTypeOf(new AllFoldedHistories(foldedGHistInfos)))
118 if (histLen > 0) {
119 update_folded_hist.getHistWithInfo(idxFhInfo).folded_hist := compute_folded_ghist(io.update.ghist, log2Ceil(nRows))
120 }
121 val update_idx = getIdx(io.update.pc, update_folded_hist)
122
123 //SCTable dual port SRAM reads and writes to the same address processing
123 // SCTable dual port SRAM reads and writes to the same address processing
124 val conflict_buffer_valid = RegInit(false.B)
125 val conflict_buffer_data = RegInit(0.U.asTypeOf(update_wdata_packed))
126 val conflict_buffer_idx = RegInit(0.U.asTypeOf(update_idx))
127 val conflict_buffer_waymask = RegInit(0.U.asTypeOf(updateWayMask))
128
124 val conflict_buffer_valid = RegInit(false.B)
125 val conflict_buffer_data = RegInit(0.U.asTypeOf(update_wdata_packed))
126 val conflict_buffer_idx = RegInit(0.U.asTypeOf(update_idx))
127 val conflict_buffer_waymask = RegInit(0.U.asTypeOf(updateWayMask))
128
129 val write_conflict = update_idx === s0_idx && io.update.mask.reduce(_||_) && io.req.valid
130 val can_write = (conflict_buffer_idx =/= s0_idx || !io.req.valid) && conflict_buffer_valid
129 val write_conflict = update_idx === s0_idx && io.update.mask.reduce(_ || _) && io.req.valid
130 val can_write = (conflict_buffer_idx =/= s0_idx || !io.req.valid) && conflict_buffer_valid
131
131
132 when(write_conflict){
132 when(write_conflict) {
133 conflict_buffer_valid := true.B
134 conflict_buffer_data := update_wdata_packed
135 conflict_buffer_idx := update_idx
136 conflict_buffer_waymask := updateWayMask
137 }
133 conflict_buffer_valid := true.B
134 conflict_buffer_data := update_wdata_packed
135 conflict_buffer_idx := update_idx
136 conflict_buffer_waymask := updateWayMask
137 }
138 when(can_write){
139 conflict_buffer_valid := false.B
138 when(can_write) {
139 conflict_buffer_valid := false.B
140 }
141
140 }
141
142 //Using buffer data for prediction
142 // Using buffer data for prediction
143 val use_conflict_data = conflict_buffer_valid && conflict_buffer_idx === s1_idx
143 val use_conflict_data = conflict_buffer_valid && conflict_buffer_idx === s1_idx
144 val conflict_data_bypass = conflict_buffer_data.zip(conflict_buffer_waymask).map {case (data, mask) => Mux(mask, data, 0.U.asTypeOf(data))}
145 val conflict_prediction_data = conflict_data_bypass.sliding(2,2).toSeq.map(VecInit(_))
146 val per_br_ctrs_unshuffled = table.io.r.resp.data.sliding(2,2).toSeq.map(VecInit(_))
147 val per_br_ctrs = VecInit((0 until numBr).map(i => Mux1H(
148 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
149 per_br_ctrs_unshuffled
150 )))
151 val conflict_br_ctrs = VecInit((0 until numBr).map(i => Mux1H(
152 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
153 conflict_prediction_data
154 )))
144 val conflict_data_bypass = conflict_buffer_data.zip(conflict_buffer_waymask).map { case (data, mask) =>
145 Mux(mask, data, 0.U.asTypeOf(data))
146 }
147 val conflict_prediction_data = conflict_data_bypass.sliding(2, 2).toSeq.map(VecInit(_))
148 val per_br_ctrs_unshuffled = table.io.r.resp.data.sliding(2, 2).toSeq.map(VecInit(_))
149 val per_br_ctrs = VecInit((0 until numBr).map(i =>
150 Mux1H(
151 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
152 per_br_ctrs_unshuffled
153 )
154 ))
155 val conflict_br_ctrs = VecInit((0 until numBr).map(i =>
156 Mux1H(
157 UIntToOH(get_phy_br_idx(s1_unhashed_idx, i), numBr),
158 conflict_prediction_data
159 )
160 ))
155
156 io.resp.ctrs := Mux(use_conflict_data, conflict_br_ctrs, per_br_ctrs)
157
158 table.io.w.apply(
161
162 io.resp.ctrs := Mux(use_conflict_data, conflict_br_ctrs, per_br_ctrs)
163
164 table.io.w.apply(
159 valid = (io.update.mask.reduce(_||_) && !write_conflict) || can_write,
165 valid = (io.update.mask.reduce(_ || _) && !write_conflict) || can_write,
160 data = Mux(can_write, conflict_buffer_data, update_wdata_packed),
161 setIdx = Mux(can_write, conflict_buffer_idx, update_idx),
162 waymask = Mux(can_write, conflict_buffer_waymask.asUInt, updateWayMask.asUInt)
163 )
164
165 val wrBypassEntries = 16
166
167 // let it corresponds to logical brIdx
166 data = Mux(can_write, conflict_buffer_data, update_wdata_packed),
167 setIdx = Mux(can_write, conflict_buffer_idx, update_idx),
168 waymask = Mux(can_write, conflict_buffer_waymask.asUInt, updateWayMask.asUInt)
169 )
170
171 val wrBypassEntries = 16
172
173 // let it corresponds to logical brIdx
168 val wrbypasses = Seq.fill(numBr)(Module(new WrBypass(SInt(ctrBits.W), wrBypassEntries, log2Ceil(nRows), numWays=2)))
174 val wrbypasses = Seq.fill(numBr)(Module(new WrBypass(SInt(ctrBits.W), wrBypassEntries, log2Ceil(nRows), numWays = 2)))
169
170 for (pi <- 0 until numBr) {
171 val br_lidx = get_lgc_br_idx(update_unhashed_idx, pi.U(log2Ceil(numBr).W))
172
173 val wrbypass_io = Mux1H(UIntToOH(br_lidx, numBr), wrbypasses.map(_.io))
174
175
176 for (pi <- 0 until numBr) {
177 val br_lidx = get_lgc_br_idx(update_unhashed_idx, pi.U(log2Ceil(numBr).W))
178
179 val wrbypass_io = Mux1H(UIntToOH(br_lidx, numBr), wrbypasses.map(_.io))
180
175 val ctrPos = Mux1H(UIntToOH(br_lidx, numBr), io.update.tagePreds)
176 val bypass_ctr = wrbypass_io.hit_data(ctrPos)
177 val previous_ctr = Mux1H(UIntToOH(br_lidx, numBr), io.update.oldCtrs)
181 val ctrPos = Mux1H(UIntToOH(br_lidx, numBr), io.update.tagePreds)
182 val bypass_ctr = wrbypass_io.hit_data(ctrPos)
183 val previous_ctr = Mux1H(UIntToOH(br_lidx, numBr), io.update.oldCtrs)
178 val hit_and_valid = wrbypass_io.hit && bypass_ctr.valid
184 val hit_and_valid = wrbypass_io.hit && bypass_ctr.valid
179 val oldCtr = Mux(hit_and_valid, bypass_ctr.bits, previous_ctr)
180 val taken = Mux1H(UIntToOH(br_lidx, numBr), io.update.takens)
185 val oldCtr = Mux(hit_and_valid, bypass_ctr.bits, previous_ctr)
186 val taken = Mux1H(UIntToOH(br_lidx, numBr), io.update.takens)
181 update_wdata(pi) := ctrUpdate(oldCtr, taken)
182 }
183
187 update_wdata(pi) := ctrUpdate(oldCtr, taken)
188 }
189
184 val per_br_update_wdata_packed = update_wdata_packed.sliding(2,2).map(VecInit(_)).toSeq
185 val per_br_update_way_mask = updateWayMask.sliding(2,2).map(VecInit(_)).toSeq
190 val per_br_update_wdata_packed = update_wdata_packed.sliding(2, 2).map(VecInit(_)).toSeq
191 val per_br_update_way_mask = updateWayMask.sliding(2, 2).map(VecInit(_)).toSeq
186 for (li <- 0 until numBr) {
187 val wrbypass = wrbypasses(li)
192 for (li <- 0 until numBr) {
193 val wrbypass = wrbypasses(li)
188 val br_pidx = get_phy_br_idx(update_unhashed_idx, li)
189 wrbypass.io.wen := io.update.mask(li)
190 wrbypass.io.write_idx := update_idx
194 val br_pidx = get_phy_br_idx(update_unhashed_idx, li)
195 wrbypass.io.wen := io.update.mask(li)
196 wrbypass.io.write_idx := update_idx
191 wrbypass.io.write_data := Mux1H(UIntToOH(br_pidx, numBr), per_br_update_wdata_packed)
192 wrbypass.io.write_way_mask.map(_ := Mux1H(UIntToOH(br_pidx, numBr), per_br_update_way_mask))
193 }
194
197 wrbypass.io.write_data := Mux1H(UIntToOH(br_pidx, numBr), per_br_update_wdata_packed)
198 wrbypass.io.write_way_mask.map(_ := Mux1H(UIntToOH(br_pidx, numBr), per_br_update_way_mask))
199 }
200
195
196 val u = io.update
201 val u = io.update
197 XSDebug(io.req.valid,
202 XSDebug(
203 io.req.valid,
198 p"scTableReq: pc=0x${Hexadecimal(io.req.bits.pc)}, " +
204 p"scTableReq: pc=0x${Hexadecimal(io.req.bits.pc)}, " +
199 p"s0_idx=${s0_idx}\n")
200 XSDebug(RegNext(io.req.valid),
205 p"s0_idx=${s0_idx}\n"
206 )
207 XSDebug(
208 RegNext(io.req.valid),
201 p"scTableResp: s1_idx=${s1_idx}," +
209 p"scTableResp: s1_idx=${s1_idx}," +
202 p"ctr:${io.resp.ctrs}\n")
203 XSDebug(io.update.mask.reduce(_||_),
210 p"ctr:${io.resp.ctrs}\n"
211 )
212 XSDebug(
213 io.update.mask.reduce(_ || _),
204 p"update Table: pc:${Hexadecimal(u.pc)}, " +
214 p"update Table: pc:${Hexadecimal(u.pc)}, " +
205 p"tageTakens:${u.tagePreds}, taken:${u.takens}, oldCtr:${u.oldCtrs}\n")
215 p"tageTakens:${u.tagePreds}, taken:${u.takens}, oldCtr:${u.oldCtrs}\n"
216 )
206}
207
208class SCThreshold(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
209 val ctr = UInt(ctrBits.W)
210 def satPos(ctr: UInt = this.ctr) = ctr === ((1.U << ctrBits) - 1.U)
211 def satNeg(ctr: UInt = this.ctr) = ctr === 0.U
212 def neutralVal = (1 << (ctrBits - 1)).U
217}
218
219class SCThreshold(val ctrBits: Int = 6)(implicit p: Parameters) extends SCBundle {
220 val ctr = UInt(ctrBits.W)
221 def satPos(ctr: UInt = this.ctr) = ctr === ((1.U << ctrBits) - 1.U)
222 def satNeg(ctr: UInt = this.ctr) = ctr === 0.U
223 def neutralVal = (1 << (ctrBits - 1)).U
213 val thres = UInt(8.W)
214 def initVal = 6.U
215 def minThres = 6.U
216 def maxThres = 31.U
224 val thres = UInt(8.W)
225 def initVal = 6.U
226 def minThres = 6.U
227 def maxThres = 31.U
217 def update(cause: Bool): SCThreshold = {
228 def update(cause: Bool): SCThreshold = {
218 val res = Wire(new SCThreshold(this.ctrBits))
229 val res = Wire(new SCThreshold(this.ctrBits))
219 val newCtr = satUpdate(this.ctr, this.ctrBits, cause)
230 val newCtr = satUpdate(this.ctr, this.ctrBits, cause)
220 val newThres = Mux(res.satPos(newCtr) && this.thres <= maxThres, this.thres + 2.U,
221 Mux(res.satNeg(newCtr) && this.thres >= minThres, this.thres - 2.U,
222 this.thres))
231 val newThres = Mux(
232 res.satPos(newCtr) && this.thres <= maxThres,
233 this.thres + 2.U,
234 Mux(res.satNeg(newCtr) && this.thres >= minThres, this.thres - 2.U, this.thres)
235 )
223 res.thres := newThres
236 res.thres := newThres
224 res.ctr := Mux(res.satPos(newCtr) || res.satNeg(newCtr), res.neutralVal, newCtr)
237 res.ctr := Mux(res.satPos(newCtr) || res.satNeg(newCtr), res.neutralVal, newCtr)
225 // XSDebug(true.B, p"scThres Update: cause${cause} newCtr ${newCtr} newThres ${newThres}\n")
226 res
227 }
228}
229
230object SCThreshold {
231 def apply(bits: Int)(implicit p: Parameters) = {
238 // XSDebug(true.B, p"scThres Update: cause${cause} newCtr ${newCtr} newThres ${newThres}\n")
239 res
240 }
241}
242
243object SCThreshold {
244 def apply(bits: Int)(implicit p: Parameters) = {
232 val t = Wire(new SCThreshold(ctrBits=bits))
233 t.ctr := t.neutralVal
245 val t = Wire(new SCThreshold(ctrBits = bits))
246 t.ctr := t.neutralVal
234 t.thres := t.initVal
235 t
236 }
237}
238
247 t.thres := t.initVal
248 t
249 }
250}
251
239
240trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
241 val update_on_mispred, update_on_unconf = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
252trait HasSC extends HasSCParameter with HasPerfEvents { this: Tage =>
253 val update_on_mispred, update_on_unconf = WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
242 var sc_fh_info = Set[FoldedHistoryInfo]()
254 var sc_fh_info = Set[FoldedHistoryInfo]()
243 if (EnableSC) {
244 val scTables = SCTableInfos.map {
245 case (nRows, ctrBits, histLen) => {
255 if (EnableSC) {
256 val scTables = SCTableInfos.map {
257 case (nRows, ctrBits, histLen) => {
246 val t = Module(new SCTable(nRows/TageBanks, ctrBits, histLen))
258 val t = Module(new SCTable(nRows / TageBanks, ctrBits, histLen))
247 val req = t.io.req
259 val req = t.io.req
248 req.valid := io.s0_fire(3)
249 req.bits.pc := s0_pc_dup(3)
260 req.valid := io.s0_fire(3)
261 req.bits.pc := s0_pc_dup(3)
250 req.bits.folded_hist := io.in.bits.folded_hist(3)
262 req.bits.folded_hist := io.in.bits.folded_hist(3)
251 req.bits.ghist := DontCare
252 if (!EnableSC) {t.io.update := DontCare}
263 req.bits.ghist := DontCare
264 if (!EnableSC) { t.io.update := DontCare }
253 t
254 }
255 }
265 t
266 }
267 }
256 sc_fh_info = scTables.map(_.getFoldedHistoryInfo).reduce(_++_).toSet
268 sc_fh_info = scTables.map(_.getFoldedHistoryInfo).reduce(_ ++ _).toSet
257
269
258 val scThresholds = List.fill(TageBanks)(RegInit(SCThreshold(5)))
270 val scThresholds = List.fill(TageBanks)(RegInit(SCThreshold(5)))
259 val useThresholds = VecInit(scThresholds map (_.thres))
260
271 val useThresholds = VecInit(scThresholds map (_.thres))
272
261 def sign(x: SInt) = x(x.getWidth-1)
262 def pos(x: SInt) = !sign(x)
263 def neg(x: SInt) = sign(x)
273 def sign(x: SInt) = x(x.getWidth - 1)
274 def pos(x: SInt) = !sign(x)
275 def neg(x: SInt) = sign(x)
264
265 def aboveThreshold(scSum: SInt, tagePvdr: SInt, threshold: UInt): Bool = {
266 val signedThres = threshold.zext
276
277 def aboveThreshold(scSum: SInt, tagePvdr: SInt, threshold: UInt): Bool = {
278 val signedThres = threshold.zext
267 val totalSum = scSum +& tagePvdr
268 (scSum > signedThres - tagePvdr) && pos(totalSum) ||
279 val totalSum = scSum +& tagePvdr
280 (scSum > signedThres - tagePvdr) && pos(totalSum) ||
269 (scSum < -signedThres - tagePvdr) && neg(totalSum)
270 }
271 val updateThresholds = VecInit(useThresholds map (t => (t << 3) +& 21.U))
272
273 val s1_scResps = VecInit(scTables.map(t => t.io.resp))
274
281 (scSum < -signedThres - tagePvdr) && neg(totalSum)
282 }
283 val updateThresholds = VecInit(useThresholds map (t => (t << 3) +& 21.U))
284
285 val s1_scResps = VecInit(scTables.map(t => t.io.resp))
286
275 val scUpdateMask = WireInit(0.U.asTypeOf(Vec(numBr, Vec(SCNTables, Bool()))))
287 val scUpdateMask = WireInit(0.U.asTypeOf(Vec(numBr, Vec(SCNTables, Bool()))))
276 val scUpdateTagePreds = Wire(Vec(TageBanks, Bool()))
288 val scUpdateTagePreds = Wire(Vec(TageBanks, Bool()))
277 val scUpdateTakens = Wire(Vec(TageBanks, Bool()))
278 val scUpdateOldCtrs = Wire(Vec(numBr, Vec(SCNTables, SInt(SCCtrBits.W))))
289 val scUpdateTakens = Wire(Vec(TageBanks, Bool()))
290 val scUpdateOldCtrs = Wire(Vec(numBr, Vec(SCNTables, SInt(SCCtrBits.W))))
279 scUpdateTagePreds := DontCare
291 scUpdateTagePreds := DontCare
280 scUpdateTakens := DontCare
281 scUpdateOldCtrs := DontCare
292 scUpdateTakens := DontCare
293 scUpdateOldCtrs := DontCare
282
283 val updateSCMeta = updateMeta.scMeta.get
284
285 val s2_sc_used, s2_conf, s2_unconf, s2_agree, s2_disagree =
286 WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
287 val update_sc_used, update_conf, update_unconf, update_agree, update_disagree =
288 WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
289 val sc_misp_tage_corr, sc_corr_tage_misp =
290 WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
291
292 // for sc ctrs
293 def getCentered(ctr: SInt): SInt = Cat(ctr, 1.U(1.W)).asSInt
294 // for tage ctrs, (2*(ctr-4)+1)*8
294
295 val updateSCMeta = updateMeta.scMeta.get
296
297 val s2_sc_used, s2_conf, s2_unconf, s2_agree, s2_disagree =
298 WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
299 val update_sc_used, update_conf, update_unconf, update_agree, update_disagree =
300 WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
301 val sc_misp_tage_corr, sc_corr_tage_misp =
302 WireInit(0.U.asTypeOf(Vec(TageBanks, Bool())))
303
304 // for sc ctrs
305 def getCentered(ctr: SInt): SInt = Cat(ctr, 1.U(1.W)).asSInt
306 // for tage ctrs, (2*(ctr-4)+1)*8
295 def getPvdrCentered(ctr: UInt): SInt = Cat(ctr ^ (1 << (TageCtrBits-1)).U, 1.U(1.W), 0.U(3.W)).asSInt
307 def getPvdrCentered(ctr: UInt): SInt = Cat(ctr ^ (1 << (TageCtrBits - 1)).U, 1.U(1.W), 0.U(3.W)).asSInt
296
297 val scMeta = resp_meta.scMeta.get
298 scMeta := DontCare
299 for (w <- 0 until TageBanks) {
300 // do summation in s2
301 val s1_scTableSums = VecInit(
302 (0 to 1) map { i =>
303 ParallelSingedExpandingAdd(s1_scResps map (r => getCentered(r.ctrs(w)(i)))) // TODO: rewrite with wallace tree
304 }
305 )
308
309 val scMeta = resp_meta.scMeta.get
310 scMeta := DontCare
311 for (w <- 0 until TageBanks) {
312 // do summation in s2
313 val s1_scTableSums = VecInit(
314 (0 to 1) map { i =>
315 ParallelSingedExpandingAdd(s1_scResps map (r => getCentered(r.ctrs(w)(i)))) // TODO: rewrite with wallace tree
316 }
317 )
306 val s2_scTableSums = RegEnable(s1_scTableSums, io.s1_fire(3))
318 val s2_scTableSums = RegEnable(s1_scTableSums, io.s1_fire(3))
307 val s2_tagePrvdCtrCentered = getPvdrCentered(RegEnable(s1_providerResps(w).ctr, io.s1_fire(3)))
319 val s2_tagePrvdCtrCentered = getPvdrCentered(RegEnable(s1_providerResps(w).ctr, io.s1_fire(3)))
308 val s2_totalSums = s2_scTableSums.map(_ +& s2_tagePrvdCtrCentered)
309 val s2_sumAboveThresholds = VecInit((0 to 1).map(i => aboveThreshold(s2_scTableSums(i), s2_tagePrvdCtrCentered, useThresholds(w))))
320 val s2_totalSums = s2_scTableSums.map(_ +& s2_tagePrvdCtrCentered)
321 val s2_sumAboveThresholds =
322 VecInit((0 to 1).map(i => aboveThreshold(s2_scTableSums(i), s2_tagePrvdCtrCentered, useThresholds(w))))
310 val s2_scPreds = VecInit(s2_totalSums.map(_ >= 0.S))
311
323 val s2_scPreds = VecInit(s2_totalSums.map(_ >= 0.S))
324
312 val s2_scResps = VecInit(RegEnable(s1_scResps, io.s1_fire(3)).map(_.ctrs(w)))
313 val s2_scCtrs = VecInit(s2_scResps.map(_(s2_tageTakens_dup(3)(w).asUInt)))
325 val s2_scResps = VecInit(RegEnable(s1_scResps, io.s1_fire(3)).map(_.ctrs(w)))
326 val s2_scCtrs = VecInit(s2_scResps.map(_(s2_tageTakens_dup(3)(w).asUInt)))
314 val s2_chooseBit = s2_tageTakens_dup(3)(w)
315
316 val s2_pred =
327 val s2_chooseBit = s2_tageTakens_dup(3)(w)
328
329 val s2_pred =
317 Mux(s2_provideds(w) && s2_sumAboveThresholds(s2_chooseBit),
318 s2_scPreds(s2_chooseBit),
319 s2_tageTakens_dup(3)(w)
320 )
330 Mux(s2_provideds(w) && s2_sumAboveThresholds(s2_chooseBit), s2_scPreds(s2_chooseBit), s2_tageTakens_dup(3)(w))
321
322 val s3_disagree = RegEnable(s2_disagree, io.s2_fire(3))
323 io.out.last_stage_spec_info.sc_disagree.map(_ := s3_disagree)
324
331
332 val s3_disagree = RegEnable(s2_disagree, io.s2_fire(3))
333 io.out.last_stage_spec_info.sc_disagree.map(_ := s3_disagree)
334
325 scMeta.scPreds(w) := RegEnable(s2_scPreds(s2_chooseBit), io.s2_fire(3))
326 scMeta.ctrs(w) := RegEnable(s2_scCtrs, io.s2_fire(3))
335 scMeta.scPreds(w) := RegEnable(s2_scPreds(s2_chooseBit), io.s2_fire(3))
336 scMeta.ctrs(w) := RegEnable(s2_scCtrs, io.s2_fire(3))
327
337
328 when (s2_provideds(w)) {
338 when(s2_provideds(w)) {
329 s2_sc_used(w) := true.B
339 s2_sc_used(w) := true.B
330 s2_unconf(w) := !s2_sumAboveThresholds(s2_chooseBit)
331 s2_conf(w) := s2_sumAboveThresholds(s2_chooseBit)
340 s2_unconf(w) := !s2_sumAboveThresholds(s2_chooseBit)
341 s2_conf(w) := s2_sumAboveThresholds(s2_chooseBit)
332 // Use prediction from Statistical Corrector
333 XSDebug(p"---------tage_bank_${w} provided so that sc used---------\n")
342 // Use prediction from Statistical Corrector
343 XSDebug(p"---------tage_bank_${w} provided so that sc used---------\n")
334 when (s2_sumAboveThresholds(s2_chooseBit)) {
335 val pred = s2_scPreds(s2_chooseBit)
344 when(s2_sumAboveThresholds(s2_chooseBit)) {
345 val pred = s2_scPreds(s2_chooseBit)
336 val debug_pc = Cat(debug_pc_s2, w.U, 0.U(instOffsetBits.W))
346 val debug_pc = Cat(debug_pc_s2, w.U, 0.U(instOffsetBits.W))
337 s2_agree(w) := s2_tageTakens_dup(3)(w) === pred
347 s2_agree(w) := s2_tageTakens_dup(3)(w) === pred
338 s2_disagree(w) := s2_tageTakens_dup(3)(w) =/= pred
339 // fit to always-taken condition
340 // io.out.s2.full_pred.br_taken_mask(w) := pred
341 XSDebug(p"pc(${Hexadecimal(debug_pc)}) SC(${w.U}) overriden pred to ${pred}\n")
342 }
343 }
344
348 s2_disagree(w) := s2_tageTakens_dup(3)(w) =/= pred
349 // fit to always-taken condition
350 // io.out.s2.full_pred.br_taken_mask(w) := pred
351 XSDebug(p"pc(${Hexadecimal(debug_pc)}) SC(${w.U}) overriden pred to ${pred}\n")
352 }
353 }
354
345 val s3_pred_dup = io.s2_fire.map(f => RegEnable(s2_pred, f))
355 val s3_pred_dup = io.s2_fire.map(f => RegEnable(s2_pred, f))
346 val sc_enable_dup = dup(RegNext(io.ctrl.sc_enable))
356 val sc_enable_dup = dup(RegNext(io.ctrl.sc_enable))
347 for (sc_enable & fp & s3_pred <-
348 sc_enable_dup zip io.out.s3.full_pred zip s3_pred_dup) {
349 when (sc_enable) {
350 fp.br_taken_mask(w) := s3_pred
351 }
357 for (
358 sc_enable & fp & s3_pred <-
359 sc_enable_dup zip io.out.s3.full_pred zip s3_pred_dup
360 ) {
361 when(sc_enable) {
362 fp.br_taken_mask(w) := s3_pred
363 }
352 }
353
354 val updateTageMeta = updateMeta
364 }
365
366 val updateTageMeta = updateMeta
355 when (updateValids(w) && updateTageMeta.providers(w).valid) {
356 val scPred = updateSCMeta.scPreds(w)
357 val tagePred = updateTageMeta.takens(w)
358 val taken = update.br_taken_mask(w)
359 val scOldCtrs = updateSCMeta.ctrs(w)
360 val pvdrCtr = updateTageMeta.providerResps(w).ctr
361 val tableSum = ParallelSingedExpandingAdd(scOldCtrs.map(getCentered))
362 val totalSumAbs = (tableSum +& getPvdrCentered(pvdrCtr)).abs.asUInt
363 val updateThres = updateThresholds(w)
367 when(updateValids(w) && updateTageMeta.providers(w).valid) {
368 val scPred = updateSCMeta.scPreds(w)
369 val tagePred = updateTageMeta.takens(w)
370 val taken = update.br_taken_mask(w)
371 val scOldCtrs = updateSCMeta.ctrs(w)
372 val pvdrCtr = updateTageMeta.providerResps(w).ctr
373 val tableSum = ParallelSingedExpandingAdd(scOldCtrs.map(getCentered))
374 val totalSumAbs = (tableSum +& getPvdrCentered(pvdrCtr)).abs.asUInt
375 val updateThres = updateThresholds(w)
364 val sumAboveThreshold = aboveThreshold(tableSum, getPvdrCentered(pvdrCtr), updateThres)
365 scUpdateTagePreds(w) := tagePred
376 val sumAboveThreshold = aboveThreshold(tableSum, getPvdrCentered(pvdrCtr), updateThres)
377 scUpdateTagePreds(w) := tagePred
366 scUpdateTakens(w) := taken
367 (scUpdateOldCtrs(w) zip scOldCtrs).foreach{case (t, c) => t := c}
378 scUpdateTakens(w) := taken
379 (scUpdateOldCtrs(w) zip scOldCtrs).foreach { case (t, c) => t := c }
368
380
369 update_sc_used(w) := true.B
370 update_unconf(w) := !sumAboveThreshold
371 update_conf(w) := sumAboveThreshold
372 update_agree(w) := scPred === tagePred
373 update_disagree(w) := scPred =/= tagePred
381 update_sc_used(w) := true.B
382 update_unconf(w) := !sumAboveThreshold
383 update_conf(w) := sumAboveThreshold
384 update_agree(w) := scPred === tagePred
385 update_disagree(w) := scPred =/= tagePred
374 sc_corr_tage_misp(w) := scPred === taken && tagePred =/= taken && update_conf(w)
375 sc_misp_tage_corr(w) := scPred =/= taken && tagePred === taken && update_conf(w)
376
377 val thres = useThresholds(w)
386 sc_corr_tage_misp(w) := scPred === taken && tagePred =/= taken && update_conf(w)
387 sc_misp_tage_corr(w) := scPred =/= taken && tagePred === taken && update_conf(w)
388
389 val thres = useThresholds(w)
378 when (scPred =/= tagePred && totalSumAbs >= thres - 4.U && totalSumAbs <= thres - 2.U) {
390 when(scPred =/= tagePred && totalSumAbs >= thres - 4.U && totalSumAbs <= thres - 2.U) {
379 val newThres = scThresholds(w).update(scPred =/= taken)
380 scThresholds(w) := newThres
381 XSDebug(p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
382 }
383
391 val newThres = scThresholds(w).update(scPred =/= taken)
392 scThresholds(w) := newThres
393 XSDebug(p"scThres $w update: old ${useThresholds(w)} --> new ${newThres.thres}\n")
394 }
395
384 when (scPred =/= taken || !sumAboveThreshold) {
396 when(scPred =/= taken || !sumAboveThreshold) {
385 scUpdateMask(w).foreach(_ := true.B)
397 scUpdateMask(w).foreach(_ := true.B)
386 XSDebug(tableSum < 0.S,
398 XSDebug(
399 tableSum < 0.S,
387 p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
400 p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
388 p"scSum(-${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
401 p"scSum(-${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
389 )
402 )
390 XSDebug(tableSum >= 0.S,
403 XSDebug(
404 tableSum >= 0.S,
391 p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
405 p"scUpdate: bank(${w}), scPred(${scPred}), tagePred(${tagePred}), " +
392 p"scSum(+${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
406 p"scSum(+${tableSum.abs}), mispred: sc(${scPred =/= taken}), tage(${updateMisPreds(w)})\n"
393 )
394 XSDebug(p"bank(${w}), update: sc: ${updateSCMeta}\n")
395 update_on_mispred(w) := scPred =/= taken
407 )
408 XSDebug(p"bank(${w}), update: sc: ${updateSCMeta}\n")
409 update_on_mispred(w) := scPred =/= taken
396 update_on_unconf(w) := scPred === taken
410 update_on_unconf(w) := scPred === taken
397 }
398 }
399 }
400
411 }
412 }
413 }
414
401
402 val realWens = scUpdateMask.transpose.map(v => v.reduce(_ | _))
403 for (b <- 0 until TageBanks) {
404 for (i <- 0 until SCNTables) {
405 val realWen = realWens(i)
415 val realWens = scUpdateMask.transpose.map(v => v.reduce(_ | _))
416 for (b <- 0 until TageBanks) {
417 for (i <- 0 until SCNTables) {
418 val realWen = realWens(i)
406 scTables(i).io.update.mask(b) := RegNext(scUpdateMask(b)(i))
419 scTables(i).io.update.mask(b) := RegNext(scUpdateMask(b)(i))
407 scTables(i).io.update.tagePreds(b) := RegEnable(scUpdateTagePreds(b), realWen)
420 scTables(i).io.update.tagePreds(b) := RegEnable(scUpdateTagePreds(b), realWen)
408 scTables(i).io.update.takens(b) := RegEnable(scUpdateTakens(b), realWen)
409 scTables(i).io.update.oldCtrs(b) := RegEnable(scUpdateOldCtrs(b)(i), realWen)
410 scTables(i).io.update.pc := RegEnable(update.pc, realWen)
411 scTables(i).io.update.ghist := RegEnable(io.update.bits.ghist, realWen)
421 scTables(i).io.update.takens(b) := RegEnable(scUpdateTakens(b), realWen)
422 scTables(i).io.update.oldCtrs(b) := RegEnable(scUpdateOldCtrs(b)(i), realWen)
423 scTables(i).io.update.pc := RegEnable(update.pc, realWen)
424 scTables(i).io.update.ghist := RegEnable(io.update.bits.ghist, realWen)
412 }
413 }
414
415 tage_perf("sc_conf", PopCount(s2_conf), PopCount(update_conf))
416 tage_perf("sc_unconf", PopCount(s2_unconf), PopCount(update_unconf))
417 tage_perf("sc_agree", PopCount(s2_agree), PopCount(update_agree))
418 tage_perf("sc_disagree", PopCount(s2_disagree), PopCount(update_disagree))
419 tage_perf("sc_used", PopCount(s2_sc_used), PopCount(update_sc_used))
420 XSPerfAccumulate("sc_update_on_mispred", PopCount(update_on_mispred))
421 XSPerfAccumulate("sc_update_on_unconf", PopCount(update_on_unconf))
422 XSPerfAccumulate("sc_mispred_but_tage_correct", PopCount(sc_misp_tage_corr))
423 XSPerfAccumulate("sc_correct_and_tage_wrong", PopCount(sc_corr_tage_misp))
424
425 }
426
427 override def getFoldedHistoryInfo = Some(tage_fh_info ++ sc_fh_info)
428
429 override val perfEvents = Seq(
430 ("tage_tht_hit ", PopCount(updateMeta.providers.map(_.valid))),
425 }
426 }
427
428 tage_perf("sc_conf", PopCount(s2_conf), PopCount(update_conf))
429 tage_perf("sc_unconf", PopCount(s2_unconf), PopCount(update_unconf))
430 tage_perf("sc_agree", PopCount(s2_agree), PopCount(update_agree))
431 tage_perf("sc_disagree", PopCount(s2_disagree), PopCount(update_disagree))
432 tage_perf("sc_used", PopCount(s2_sc_used), PopCount(update_sc_used))
433 XSPerfAccumulate("sc_update_on_mispred", PopCount(update_on_mispred))
434 XSPerfAccumulate("sc_update_on_unconf", PopCount(update_on_unconf))
435 XSPerfAccumulate("sc_mispred_but_tage_correct", PopCount(sc_misp_tage_corr))
436 XSPerfAccumulate("sc_correct_and_tage_wrong", PopCount(sc_corr_tage_misp))
437
438 }
439
440 override def getFoldedHistoryInfo = Some(tage_fh_info ++ sc_fh_info)
441
442 override val perfEvents = Seq(
443 ("tage_tht_hit ", PopCount(updateMeta.providers.map(_.valid))),
431 ("sc_update_on_mispred ", PopCount(update_on_mispred) ),
432 ("sc_update_on_unconf ", PopCount(update_on_unconf) ),
444 ("sc_update_on_mispred ", PopCount(update_on_mispred)),
445 ("sc_update_on_unconf ", PopCount(update_on_unconf))
433 )
434 generatePerfEvent()
435}
446 )
447 generatePerfEvent()
448}