SimTop.scala (2993c5ecece73b73073301e23435ca1b763d0b5f) SimTop.scala (78a8cd257caa1ff2b977d80082b1b3a2fa98a1d3)
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

--- 23 unchanged lines hidden (view full) ---

32 val debugOpts = p(DebugOptionsKey)
33
34 val l_soc = LazyModule(new XSTop())
35 val soc = Module(l_soc.module)
36 // Don't allow the top-level signals to be optimized out,
37 // so that we can re-use this SimTop for any generated Verilog RTL.
38 dontTouch(soc.io)
39
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
4* Copyright (c) 2020-2021 Peng Cheng Laboratory
5*
6* XiangShan is licensed under Mulan PSL v2.
7* You can use this software according to the terms and conditions of the Mulan PSL v2.
8* You may obtain a copy of Mulan PSL v2 at:

--- 23 unchanged lines hidden (view full) ---

32 val debugOpts = p(DebugOptionsKey)
33
34 val l_soc = LazyModule(new XSTop())
35 val soc = Module(l_soc.module)
36 // Don't allow the top-level signals to be optimized out,
37 // so that we can re-use this SimTop for any generated Verilog RTL.
38 dontTouch(soc.io)
39
40 l_soc.module.dma.get <> 0.U.asTypeOf(l_soc.module.dma.get)
40 if (!l_soc.module.dma.isEmpty) {
41 l_soc.module.dma.get <> 0.U.asTypeOf(l_soc.module.dma.get)
42 }
41
43
42 val l_simMMIO = LazyModule(new SimMMIO(l_soc.socMisc.get.peripheralNode.in.head._2))
44 val l_simMMIO = LazyModule(new SimMMIO(l_soc.nocMisc.get.peripheralNode.in.head._2))
43 val simMMIO = Module(l_simMMIO.module)
44 l_simMMIO.io_axi4.elements.head._2 <> soc.peripheral.get.viewAs[AXI4Bundle]
45
46 val l_simAXIMem = AXI4MemorySlave(
47 l_soc.misc.memAXI4SlaveNode,
48 16L * 1024 * 1024 * 1024,
49 useBlackBox = true,
50 dynamicLatency = debugOpts.UseDRAMSim

--- 71 unchanged lines hidden --- 		45 val simMMIO = Module(l_simMMIO.module)
46 l_simMMIO.io_axi4.elements.head._2 <> soc.peripheral.get.viewAs[AXI4Bundle]
47
48 val l_simAXIMem = AXI4MemorySlave(
49 l_soc.misc.memAXI4SlaveNode,
50 16L * 1024 * 1024 * 1024,
51 useBlackBox = true,
52 dynamicLatency = debugOpts.UseDRAMSim

--- 71 unchanged lines hidden ---