fix(device, DebugMoudle): do not use clock with Bool type (#4152)

* gsim can not handle such clocks

submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint

XSLog depends on LogPerfCtrl declared at Top Module. Previous we
annotate such signal as dontTouch, and accessed through Hier

submodule(utility), transforms: collect XSLogs to SimTop.LogPerfEndpoint

XSLog depends on LogPerfCtrl declared at Top Module. Previous we
annotate such signal as dontTouch, and accessed through Hierarchical
name like SimTop.xx by dummy LogPerfHelper.

However, as XSLog is called in many spaces in DUT, which are not
visible to each other, especailly some in WhenContext. XS will generate
thousands of LogPerfHelper to get same LogPerfCtrl. Too many module
instantiations greately slow down compilation speed, especailly in
Palladium (more than 5 times slower than same DUT without Log).

This change collect all XSLog to SimTop.LogPerfEndpoint, with
LogPerfCtrl directly passed by IO. Some tips as follows:

1. Not call XSLog inside whenContext. To collect XSLogs, we should
access Cond and Data from other module, but data in WhenContext is
not accessible even through tap. Use XSLog(cond, pable) instead of
when(cond) {XSLog(pable)}. We also add chisel Internal API currentWhen
to check that.

2. Generate Hierarchical Module path through FIRRTL transforms.
Sometimes we want to append module path for better debugging.
XSCompatibility add a hacky way to use Chisel internal API to get
tag of current Module. Then we will replace these tag with
path during ChiselStage. Note path can only be acessed after circuit
elaboration.

3. Register and invoke caller of XSPerf and related object. As XSPerf
depends on LogPerfCtrl such as dump. We should deferred apply() until
collect. So we regirster collect() method when firstly apply XSLog,
then XSLog will automatically call XSPerf.collect() method during
collection. Note deferred apply is called in another module, so original
module tag should be recorded for path generation.

4. Concat XSLogs with same condition. Too many fwrites in same module
will cause UPOPTTHREADS warning with 16-threads Verilator. Consider
many XSLogs have same condition (especailly XSPerfs), we reuse same
condition and concat their printables to reduce fwrites. Note we also
limit size of concatation to 1000 to avoid segmentation fault caused
by too long printf.

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feat(trace): add TraceCoreInterface in top.

fix(SimTop): Set sim memory size same as PMA (#3750)

fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the

fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the core will hang. This commit use fine-grained on-chip MMIO ranges so
that memory accessing of these holes will be routed out of core and
handled by other mechanisms.

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fix(Smrnmi): expand NMI interrupt to two types and route the nmi signals to XSTOP (#3691)

chore: bump chisel 6.5.0 (#3210)

SoC, Top: use Option for SoC widgets concerning L3

SoC: an initial version of DummyLLC

Top: use VerilogAXI4Record instead of `sed` to handle amba signal names

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect down

Add CoupledL2 with CHI interface (#2953)

This pull request introduces TL2CHICoupledL2, which adopts TileLink
standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification
to connect downstream interconnect. The key features of TL2CHICoupledL2
are:
* Fully coherent Request Node in a CHI interconnect.
* Coherency granule of 64B cache line.
* MESI cache coherence model, which is based on TileLink coherence
policies.
* Transition from TL-C transactions to CHI snoopable requests.
* Transition from TL-UL transactions to CHI non-snoopable requests.
* Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique.
* Support for WriteNoSnp, WriteBackFull, Evict.
* Support for all the snoops except for SnpDVMOp.
* Request retry to manage protocol resources.
* Message transfer across CHI interfaces based on Link Layer Credit.
* Power aware signaling on the component interface.

The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2
still works as default L2 Cache instance in
[XiangShan](https://github.com/OpenXiangShan/XiangShan) processor for
now. TL2CHICoupledL2 is still not available for verilator simulation in
this pr.

To compile XSTile verilog with TL2CHICoupledL2, run `make verilog
CONFIG=KunminghuV2Config RELEASE_ARGS MFC=1`.

---------

Signed-off-by: Yangyu Chen <[email protected]>
Co-authored-by: Zhu Yu <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
Co-authored-by: Yangyu Chen <[email protected]>

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Merge remote-tracking branch 'upstream/kunminghu' into tmp-backend-merge-master

Bump difftest (#2579)

Merge remote-tracking branch 'upstream/master' into backendq

Debug Module: cherry-pick debug module from nanhu

Bump difftest (#2391)

* use the abstract DifftestMem class
* move DifftestModule.finish to hardware

build: support chisel 3.6.0 and chisel 6.0.0-M3 (#2372)

chore: bump rocket, Scala 2.13.10, and Chisel 3.6.0 (#2326)

Co-authored-by: Yinan Xu <[email protected]>

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

log: use XMR instead of boring utils for logging (#2302)

Bump difftest for Chisel-generated interfaces (#2284)

We also add support for difftest with RISC-V Vector extension and nFused.

L2 TLB check is disabled unexpectedly and will be fixed soon.

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump hua

Disable chiselDB by default to minimize the size of DB (#2118)

* config: disable chiseldb by default to minimize db size

* note that tllog is still enabled when alwaysBasicDB is set

* bump huancun & utility

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Fix constant (#2071)

* constant: fix dead loop

* util: fix constant dynamic switch

* util: fix constant

circt: fix assertion fails in circt simulation (#2023)