1/*************************************************************************************** 2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4* Copyright (c) 2020-2021 Peng Cheng Laboratory 5* 6* XiangShan is licensed under Mulan PSL v2. 7* You can use this software according to the terms and conditions of the Mulan PSL v2. 8* You may obtain a copy of Mulan PSL v2 at: 9* http://license.coscl.org.cn/MulanPSL2 10* 11* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14* 15* See the Mulan PSL v2 for more details. 16***************************************************************************************/ 17 18package top 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.util._ 23import chisel3.experimental.dataview._ 24import device.{AXI4MemorySlave, SimJTAG} 25import difftest._ 26import freechips.rocketchip.amba.axi4.AXI4Bundle 27import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule} 28import freechips.rocketchip.util.HeterogeneousBag 29import utility.{ChiselDB, Constantin, FileRegisters, GTimer, XSLog} 30import xiangshan.DebugOptionsKey 31import system.SoCParamsKey 32 33class SimTop(implicit p: Parameters) extends Module { 34 val debugOpts = p(DebugOptionsKey) 35 36 val l_soc = LazyModule(new XSTop()) 37 val soc = Module(l_soc.module) 38 // Don't allow the top-level signals to be optimized out, 39 // so that we can re-use this SimTop for any generated Verilog RTL. 40 dontTouch(soc.io) 41 42 if (!l_soc.module.dma.isEmpty) { 43 l_soc.module.dma.get <> WireDefault(0.U.asTypeOf(l_soc.module.dma.get)) 44 } 45 46 val l_simMMIO = LazyModule(new SimMMIO(l_soc.misc.peripheralNode.in.head._2)(p.alter((site, here, up) => { 47 case SoCParamsKey => up(SoCParamsKey).copy(UARTLiteForDTS = false) 48 }))) 49 val simMMIO = Module(l_simMMIO.module) 50 l_simMMIO.io_axi4.elements.head._2 <> soc.peripheral.viewAs[AXI4Bundle] 51 52 val l_simAXIMem = AXI4MemorySlave( 53 l_soc.misc.memAXI4SlaveNode, 54 8190L * 1024 * 1024 * 1024, 55 useBlackBox = true, 56 dynamicLatency = debugOpts.UseDRAMSim 57 ) 58 val simAXIMem = Module(l_simAXIMem.module) 59 l_simAXIMem.io_axi4.elements.head._2 :<>= soc.memory.viewAs[AXI4Bundle].waiveAll 60 61 soc.io.clock := clock 62 soc.io.reset := (reset.asBool || soc.io.debug_reset).asAsyncReset 63 soc.io.extIntrs := simMMIO.io.interrupt.intrVec 64 soc.io.sram_config := 0.U 65 soc.io.pll0_lock := true.B 66 soc.io.cacheable_check := DontCare 67 soc.io.riscv_rst_vec.foreach(_ := 0x10000000L.U) 68 l_soc.nmi.foreach(_.foreach(intr => { intr := false.B; dontTouch(intr) })) 69 soc.io.traceCoreInterface.foreach(_.fromEncoder.enable := false.B) 70 soc.io.traceCoreInterface.foreach(_.fromEncoder.stall := false.B) 71 72 // soc.io.rtc_clock is a div100 of soc.io.clock 73 val rtcClockDiv = 100 74 val rtcTickCycle = rtcClockDiv / 2 75 val rtcCounter = RegInit(0.U(log2Ceil(rtcTickCycle + 1).W)) 76 rtcCounter := Mux(rtcCounter === (rtcTickCycle - 1).U, 0.U, rtcCounter + 1.U) 77 val rtcClock = RegInit(false.B) 78 when (rtcCounter === 0.U) { 79 rtcClock := ~rtcClock 80 } 81 soc.io.rtc_clock := rtcClock 82 83 val success = Wire(Bool()) 84 val jtag = Module(new SimJTAG(tickDelay = 3)(p)) 85 jtag.connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success) 86 soc.io.systemjtag.reset := reset.asAsyncReset 87 soc.io.systemjtag.mfr_id := 0.U(11.W) 88 soc.io.systemjtag.part_number := 0.U(16.W) 89 soc.io.systemjtag.version := 0.U(4.W) 90 91 val difftest = DifftestModule.finish("XiangShan") 92 93 simMMIO.io.uart <> difftest.uart 94 95 val hasPerf = !debugOpts.FPGAPlatform && debugOpts.EnablePerfDebug 96 val hasLog = !debugOpts.FPGAPlatform && debugOpts.EnableDebug 97 val hasPerfLog = hasPerf || hasLog 98 val timer = if (hasPerfLog) GTimer() else WireDefault(0.U(64.W)) 99 val logEnable = if (hasPerfLog) WireDefault(difftest.logCtrl.enable(timer)) else WireDefault(false.B) 100 val clean = if (hasPerf) WireDefault(difftest.perfCtrl.clean) else WireDefault(false.B) 101 val dump = if (hasPerf) WireDefault(difftest.perfCtrl.dump) else WireDefault(false.B) 102 103 XSLog.collect(timer, logEnable, clean, dump) 104} 105 106object SimTop extends App { 107 // Keep this the same as TopMain except that SimTop is used here instead of XSTop 108 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 109 110 // tools: init to close dpi-c when in fpga 111 val envInFPGA = config(DebugOptionsKey).FPGAPlatform 112 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB 113 val enableConstantin = config(DebugOptionsKey).EnableConstantin 114 Constantin.init(enableConstantin && !envInFPGA) 115 ChiselDB.init(enableChiselDB && !envInFPGA) 116 117 Generator.execute( 118 firrtlOpts, 119 DisableMonitors(p => new SimTop()(p))(config), 120 firtoolOpts 121 ) 122 123 // tools: write cpp files 124 ChiselDB.addToFileRegisters 125 Constantin.addToFileRegisters 126 FileRegisters.write(fileDir = "./build") 127} 128