SimTop.scala (7f37d55fc418d3b4583220e634da7e459802c6d8) SimTop.scala (51e45dbbf87325e45ff2af6ca86ed6c7eed04464)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 8 unchanged lines hidden (view full) ---

17package top
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import device.{AXI4MemorySlave, SimJTAG}
23import difftest._
24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule}
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8* http://license.coscl.org.cn/MulanPSL2

--- 8 unchanged lines hidden (view full) ---

17package top
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import device.{AXI4MemorySlave, SimJTAG}
23import difftest._
24import freechips.rocketchip.diplomacy.{DisableMonitors, LazyModule}
25import utility.FileRegisters
26import utility.ChiselDB
27import utility.GTimer
25import utility.{ChiselDB, Constantin, FileRegisters, GTimer}
28import xiangshan.DebugOptionsKey
26import xiangshan.DebugOptionsKey
29import utility.Constantin
30
31class SimTop(implicit p: Parameters) extends Module {
32 val debugOpts = p(DebugOptionsKey)
33
34 val l_soc = LazyModule(new XSTop())
35 val soc = Module(l_soc.module)
36 // Don't allow the top-level signals to be optimized out,
37 // so that we can re-use this SimTop for any generated Verilog RTL.

--- 59 unchanged lines hidden (view full) ---

97 dontTouch(timer)
98 dontTouch(logEnable)
99 dontTouch(clean)
100 dontTouch(dump)
101}
102
103object SimTop extends App {
104 // Keep this the same as TopMain except that SimTop is used here instead of XSTop
27
28class SimTop(implicit p: Parameters) extends Module {
29 val debugOpts = p(DebugOptionsKey)
30
31 val l_soc = LazyModule(new XSTop())
32 val soc = Module(l_soc.module)
33 // Don't allow the top-level signals to be optimized out,
34 // so that we can re-use this SimTop for any generated Verilog RTL.

--- 59 unchanged lines hidden (view full) ---

94 dontTouch(timer)
95 dontTouch(logEnable)
96 dontTouch(clean)
97 dontTouch(dump)
98}
99
100object SimTop extends App {
101 // Keep this the same as TopMain except that SimTop is used here instead of XSTop
105 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args)
102 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
106
107 // tools: init to close dpi-c when in fpga
108 val envInFPGA = config(DebugOptionsKey).FPGAPlatform
109 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
110 val enableConstantin = config(DebugOptionsKey).EnableConstantin
111 Constantin.init(enableConstantin && !envInFPGA)
112 ChiselDB.init(enableChiselDB && !envInFPGA)
113
114 Generator.execute(
115 firrtlOpts,
116 DisableMonitors(p => new SimTop()(p))(config),
103
104 // tools: init to close dpi-c when in fpga
105 val envInFPGA = config(DebugOptionsKey).FPGAPlatform
106 val enableChiselDB = config(DebugOptionsKey).EnableChiselDB
107 val enableConstantin = config(DebugOptionsKey).EnableConstantin
108 Constantin.init(enableConstantin && !envInFPGA)
109 ChiselDB.init(enableChiselDB && !envInFPGA)
110
111 Generator.execute(
112 firrtlOpts,
113 DisableMonitors(p => new SimTop()(p))(config),
117 firrtlComplier,
118 firtoolOpts
119 )
120
121 // tools: write cpp files
122 ChiselDB.addToFileRegisters
123 Constantin.addToFileRegisters
124 FileRegisters.write(fileDir = "./build")
125 DifftestModule.finish("XiangShan")
126}
114 firtoolOpts
115 )
116
117 // tools: write cpp files
118 ChiselDB.addToFileRegisters
119 Constantin.addToFileRegisters
120 FileRegisters.write(fileDir = "./build")
121 DifftestModule.finish("XiangShan")
122}