DecodeTest.scala (4b0d80d87574e82ba31737496d63ac30bed0d40a) DecodeTest.scala (51e45dbbf87325e45ff2af6ca86ed6c7eed04464)
1package xiangshan
2
3import chisel3._
1package xiangshan
2
3import chisel3._
4import chisel3.stage._
4import chisel3.stage.ChiselGeneratorAnnotation
5import chiseltest._
5import chiseltest._
6import chiseltest.ChiselScalatestTester
7import chiseltest.VerilatorBackendAnnotation
6import chiseltest.VerilatorBackendAnnotation
8import chiseltest.simulator.{VerilatorFlags, VerilatorCFlags}
9import org.scalatest.flatspec.AnyFlatSpec
10import org.scalatest.matchers.must.Matchers
11import firrtl.stage.RunFirrtlTransformAnnotation
12import xstransforms.PrintModuleName
13import firrtl.options.TargetDirAnnotation
7import chiseltest.simulator.VerilatorFlags
14import top.ArgParser
8import top.ArgParser
15import utility.FileRegisters
16import xiangshan.backend.decode.DecodeUnit
9import xiangshan.backend.decode.DecodeUnit
17import xiangshan.backend.regfile.IntPregParams
10import types.ChiselStage
11import xiangshan.test.types._
12import xiangshan.types.PrintModuleName
18
19object DecodeMain extends App {
13
14object DecodeMain extends App {
20 val (config, firrtlOpts, firrtlComplier, firtoolOpts) = ArgParser.parse(args)
15 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args)
21 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
22 // If Complex Params are needed, wrap it with a Top Module to do dirty works,
23 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params"
24 val defaultConfig = config.alterPartial({
25 // Get XSCoreParams and pass it to the "small module"
26 case XSCoreParamsKey => config(XSTileKey).head.copy(
27 // Example of how to change params
16 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
17 // If Complex Params are needed, wrap it with a Top Module to do dirty works,
18 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params"
19 val defaultConfig = config.alterPartial({
20 // Get XSCoreParams and pass it to the "small module"
21 case XSCoreParamsKey => config(XSTileKey).head.copy(
22 // Example of how to change params
28 intPreg = IntPregParams(
29 numEntries = 64,
30 numRead = Some(14),
31 numWrite = Some(8),
32 ),
23 IssQueSize = 12
33 )
34 })
35 (new ChiselStage).execute(args, Seq(
36 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig)
37 )))
38// // Generate files when compiling. Used by ChiselDB.
39// FileRegisters.write("./build")
40}
41
42class DecodeUnitTest extends XSTester {
43 behavior of "DecodeUnit"
44 it should "pass" in {
24 )
25 })
26 (new ChiselStage).execute(args, Seq(
27 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig)
28 )))
29// // Generate files when compiling. Used by ChiselDB.
30// FileRegisters.write("./build")
31}
32
33class DecodeUnitTest extends XSTester {
34 behavior of "DecodeUnit"
35 it should "pass" in {
36 val printModuleNameAnno = chisel3.BuildInfo.version match {
37 case "3.6.0" => Seq(RunFirrtlTransformAnnotation(new PrintModuleName))
38 case _ => Seq()
39 }
40
45 test(new DecodeUnit()(config)).withAnnotations(Seq(
46 VerilatorBackendAnnotation,
47 VerilatorFlags(Seq()),
48 WriteVcdAnnotation,
41 test(new DecodeUnit()(config)).withAnnotations(Seq(
42 VerilatorBackendAnnotation,
43 VerilatorFlags(Seq()),
44 WriteVcdAnnotation,
49 TargetDirAnnotation("./build"),
50 RunFirrtlTransformAnnotation(new PrintModuleName)
51 )){ dut =>
45 TargetDirAnnotation("./build")
46 ) ++ printModuleNameAnno){ dut =>
52 dut.clock.step(10)
53 }
54 }
55}
47 dut.clock.step(10)
48 }
49 }
50}