| #
e3da8bad |
| 22-Jul-2024 |
Tang Haojin <[email protected]> |
build: purge chisel 3 and add deprecation check (#3250)
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| #
8241cb85 |
| 17-Dec-2023 |
Xuan Hu <[email protected]> |
Merge remote-tracking branch 'upstream/master' into backendq
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| #
5931ace3 |
| 26-Oct-2023 |
Tang Haojin <[email protected]> |
refactor directory hierarchy for two chisel versions (#2423)
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| #
da50abf9 |
| 25-Oct-2023 |
Tang Haojin <[email protected]> |
xstransform: support PrintControl and PrintModuleName for chisel6 (#2422)
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| #
c7d010e5 |
| 12-Oct-2023 |
Xuan Hu <[email protected]> |
Merge upstream/master into new-backend
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| #
51e45dbb |
| 11-Oct-2023 |
Tang Haojin <[email protected]> |
build: support chisel 3.6.0 and chisel 6.0.0-M3 (#2372)
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| #
4b0d80d8 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
Merge upstream/master into tmp-backend-merge-master
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| #
7f37d55f |
| 09-Oct-2023 |
Tang Haojin <[email protected]> |
chore: bump rocket, Scala 2.13.10, and Chisel 3.6.0 (#2326)
Co-authored-by: Yinan Xu <[email protected]>
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| #
39c59369 |
| 03-Aug-2023 |
Xuan Hu <[email protected]> |
params,backend: refactor RegFile parameters
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| #
8a00ff56 |
| 21-Apr-2023 |
Xuan Hu <[email protected]> |
backend: fix merge master error
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| #
b665b650 |
| 04-Apr-2023 |
Tang Haojin <[email protected]> |
circt: fix assertion fails in circt simulation (#2023)
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| #
876196b7 |
| 19-Mar-2023 |
Maxpicca-Li <[email protected]> |
util: change ElaborationArtefacts to FileRegisters (#1973)
* util: change ElaborationArtefacts to FileRegisters
use `filename` instead of `extension` to record file
* huancun: merge master
util: change ElaborationArtefacts to FileRegisters (#1973)
* util: change ElaborationArtefacts to FileRegisters
use `filename` instead of `extension` to record file
* huancun: merge master
* huancun: version change
* util: update to main
* SimTop: delete unused comment
* constantin: fix bug which reduced emputy map
* code opt: add write api in FileRegisters
show more ...
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| #
51981c77 |
| 14-Feb-2023 |
bugGenerator <[email protected]> |
test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argp
test: add example of chiseltest's unit-test and generating verilog for xs' module (#1890)
* test: add example to genenrate verilog for a small module
Just use Parameters from DefaultConfig(& Argparser) like XSTop/SimTop
* test: add DecodeUnitTest as an example for xs' chiseltest
* ctrlblock: <> usage has changed, unidirection should use :=
* bump huancun
* makefile: mv new makefile cmd into Makefile.test
show more ...
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