1package xiangshan 2 3import chisel3._ 4import chisel3.stage.ChiselGeneratorAnnotation 5import chiseltest._ 6import chiseltest.VerilatorBackendAnnotation 7import chiseltest.simulator.VerilatorFlags 8import top.ArgParser 9import xiangshan.backend.decode.DecodeUnit 10import xiangshan.backend.regfile.IntPregParams 11import circt.stage.ChiselStage 12import firrtl2.options.TargetDirAnnotation 13import xiangshan.transforms.PrintModuleName 14 15object DecodeMain extends App { 16 val (config, firrtlOpts, firtoolOpts) = ArgParser.parse(args) 17 // //val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config) 18 // If Complex Params are needed, wrap it with a Top Module to do dirty works, 19 // and use "chisel3.aop.Select.collectDeep[ModuleWanted](WrapperModule){case a: ModuleWanted => a}.head.Params" 20 val defaultConfig = config.alterPartial({ 21 // Get XSCoreParams and pass it to the "small module" 22 case XSCoreParamsKey => config(XSTileKey).head.copy( 23 // Example of how to change params 24 intPreg = IntPregParams( 25 numEntries = 64, 26 numRead = Some(14), 27 numWrite = Some(8), 28 ), 29 ) 30 }) 31 (new ChiselStage).execute(args, Seq( 32 ChiselGeneratorAnnotation(() => new DecodeUnit()(defaultConfig) 33 ))) 34// // Generate files when compiling. Used by ChiselDB. 35// FileRegisters.write("./build") 36} 37 38class DecodeUnitTest extends XSTester { 39 behavior of "DecodeUnit" 40 it should "pass" in { 41 test(new DecodeUnit()(config)).withAnnotations(Seq( 42 VerilatorBackendAnnotation, 43 VerilatorFlags(Seq()), 44 WriteVcdAnnotation, 45 TargetDirAnnotation("./build") 46 )){ dut => 47 dut.clock.step(10) 48 } 49 } 50} 51