ci: search numactl process to avoid conflicts (#3276)

ci: add basic ci for Hypervisor extension (#3273)

This patch add xvisor_wboxtest to ci, which tests the nested mmu system.
riscv-hyp-tests are still on the way.

ci: add ci for V extension (#3268)

This commit add simple ci tests for V extension.

build: purge chisel 3 and add deprecation check (#3250)

script: add `gcpt-restore-bin` arg to specify the gcpt restore bin

CI: modify bbl-based SMP linux `bbl.bin`

* exp[breakpoint] can't be delegated when trigger enable

chore: bump chisel 6.5.0 (#3210)

ci: fix vcs ci when it do not exit normally (#3141)

CI: enable PGO when building emu for CI (#3080)

ci: add simple xprop test through vcs (#3071)

ci: use faster bbl-based SMP linux 4.18.0 (#3049)

ci: disable '-O3' for verilator when running MC (#3002)

CI: switch to opensbi for linux-hello & switch to mfc for MC (#2836)

* CI: switch to opensbi for linux-hello tests

We have discoverd that the older version of riscv-pk crashes on harts that suppo

CI: switch to opensbi for linux-hello & switch to mfc for MC (#2836)

* CI: switch to opensbi for linux-hello tests

We have discoverd that the older version of riscv-pk crashes on harts that support H-ext due to issues with checking mideleg. Although this issue was fixed back in 2021 (commit 4ae5a88), considering that riscv-pk has been replaced by opensbi, we deciede to gradually transition our testing workloads to utilize opensbi instead.

* CI: use MFC for EMU - MC test

Using MFC for EMU - MC test may decrease the total ci time.

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chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`

Makefile: download firtool if it is not in PATH (#2398)

ci: add ci for chisel6 (#2374)

* ci: add ci for chisel6

* ci: specify firtool path

* scripts: enlarge stack size when running emu

* ci: remove MC CI for MFC

Bump difftest for Chisel-generated interfaces (#2284)

We also add support for difftest with RISC-V Vector extension and nFused.

L2 TLB check is disabled unexpectedly and will be fixed soon.

script: enable chiseldb by default on running emu by xiangshan.py (#2091)

* script: enable chiseldb by default on running emu by xiangshan.py

* script: move db file to wave_home if emu failed

Tool: cancel DIP-C write when in FPGA (#2009)

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

Tool: cancel DIP-C write when in FPGA (#2009)

* constant variable: add FPAGPlatform parameter

* scripts: set WITH_CONSTANTIN to 1 by default

* submodules: version to lyq repository for test

* Revert "constant variable: add FPAGPlatform parameter"

This reverts commit fc2f03b768cb2ad63cb543096b00b971c85467d6.

* constant: add FPGA init

* chiseldb: add FPGA init

* difftest: version

* chisledb: add envFPGA situation

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LoadMissTable: add it and use constant control (#1969)

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the const

LoadMissTable: add it and use constant control (#1969)

* DCacheWrapper: add missdb and fix bug in `real_miss`

* DCacheWrapper: add constant control of missdb

* DCacheWrapper: correct the constant control logic

* databases: add constant control

* constantin: afix some bug

* constantin: fix txt

* fixbug: constant control in double core

* constantin: postfix changed in `verilator.mk`

* instDB: add robIdx and some TIME signals

* loadMissDB-copt: rm `resp.bits.firstHit` add `s2_first_hit`

* difftest: update

* yml: update the git workflow

* submodules: fix the binding commit-id of personal fork rep

* fix: github workflow add NOOP_HOME

because in constantin.scala use the absolute path of workdir by environment variable `NOOP_HOME`

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Bump difftest to fix resource leak problem (#1866)

ci: add extra pmp test

Add FST waveform support (#1804)

Usage:

When make emu, please use EMU_TRACE=1, EMU_TRACE=vcd or EMU_TRACE=VCD
to dump waveform of vcd format, and use EMU_TRACE=fst or EMU_TRACE=FST
to dump wave

Add FST waveform support (#1804)

Usage:

When make emu, please use EMU_TRACE=1, EMU_TRACE=vcd or EMU_TRACE=VCD
to dump waveform of vcd format, and use EMU_TRACE=fst or EMU_TRACE=FST
to dump waveform of fst format.

When use xiangshan.py, please add --trace to dump waveform of vcd format,
and add --trace-fst to dump waveform of fst format.

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CI: support basic VCS simulation (#1575)

* bump difftest

* ci: support basic simv emulation

* ci: use exact ip address to ssh

* ci: modify simv emulation timeout threshold

Fix vcs simulation support, support manually set ram_size (#1551)

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-

Fix vcs simulation support, support manually set ram_size (#1551)

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

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