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8cfc24b2 |
| 07-Apr-2025 |
Tang Haojin <[email protected]> |
feat(AIA): integrate ChiselAIA again (#4509)
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529b1cfd |
| 17-Mar-2025 |
Tang Haojin <[email protected]> |
Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)
This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.
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7fbc1cb4 |
| 08-Mar-2025 |
Tang Haojin <[email protected]> |
feat(AIA): integrate ChiselAIA (#4378)
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af3eaba0 |
| 17-Oct-2024 |
Tang Haojin <[email protected]> |
timing(IMSIC): AXI4 output should be buffered (#3757)
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18560912 |
| 27-Sep-2024 |
Tang Haojin <[email protected]> |
fix(IMSIC): add TLBuffer for tilelink IO (#3668)
It is better for Top IO to be register out. Add TLBuffer for TileLink
version of IMSIC.
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468d6533 |
| 13-Sep-2024 |
Tang Haojin <[email protected]> |
feat(IMSIC): change tl source width to 4 (#3529)
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9143e232 |
| 12-Sep-2024 |
Jiuyue Ma <[email protected]> |
feat(IMSIC): combine M/S mode axi4lite ports into single port (#3519)
Signed-off-by: Jiuyue Ma <[email protected]>
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f835884f |
| 19-Jul-2024 |
Haojin Tang <[email protected]> |
AIA: use sv suffix for AIA modules
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720dd621 |
| 04-Jul-2024 |
Tang Haojin <[email protected]> |
top: implement XSNoCTop and standalone devices (#3136)
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