xref: /XiangShan/src/main/scala/device/imsic_axi_top.scala (revision 8cfc24b28454f1915c339ce79485711f8e438f59) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package device
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config.Parameters
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.amba.axi4._
24import freechips.rocketchip.tilelink._
25import system.HasSoCParameter
26
27object IMSICBusType extends Enumeration {
28  val NONE, TL, AXI = Value
29}
30
31class imsic_bus_top(implicit p: Parameters) extends LazyModule with HasSoCParameter {
32  // Tilelink Bus
33  val tl_reg_imsic = Option.when(soc.IMSICBusType == device.IMSICBusType.TL)(LazyModule(new aia.TLRegIMSIC(soc.IMSICParams, seperateBus = true)))
34
35  val tl = tl_reg_imsic.map { tl_reg_imsic =>
36    val tlnodes = Seq.fill(2)(TLClientNode(Seq(TLMasterPortParameters.v1(
37      clients = Seq(TLMasterParameters.v1(
38        "tl",
39        sourceId = IdRange(0, 65536)
40      ))
41    ))))
42    tl_reg_imsic.fromMem zip tlnodes foreach { case (fromMem, tlnode) =>
43      fromMem :=
44        TLWidthWidget(4) :=
45        TLFIFOFixer() :=
46        TLBuffer() :=
47        tlnode
48    }
49    tlnodes
50  }
51
52  val tl_m = tl.map(x => InModuleBody(x(0).makeIOs()))
53  val tl_s = tl.map(x => InModuleBody(x(1).makeIOs()))
54
55  // AXI4 Bus
56  val axi_reg_imsic = Option.when(soc.IMSICBusType == device.IMSICBusType.AXI)(LazyModule(new aia.AXIRegIMSIC(soc.IMSICParams, seperateBus = false)))
57
58  val axi = axi_reg_imsic.map { axi_reg_imsic =>
59    val axinode = AXI4MasterNode(Seq(AXI4MasterPortParameters(
60      Seq(AXI4MasterParameters(
61        name = "s_axi_",
62        id = IdRange(0, 65536)
63      ))
64    )))
65    axi_reg_imsic.axi4tolite.head.node := AXI4Buffer() := axinode
66    axinode
67  }
68
69  val axi4 = axi.map(x => InModuleBody(x.makeIOs()))
70
71  class imsic_bus_top_imp(wrapper: imsic_bus_top) extends LazyModuleImp(wrapper) {
72    val msiio = IO(Flipped(new aia.MSITransBundle(soc.IMSICParams)))
73
74    // No Bus
75    val msi = Option.when(soc.IMSICBusType == device.IMSICBusType.NONE)(
76      IO(new aia.MSITransBundle(soc.IMSICParams))
77    )
78
79    tl_reg_imsic.foreach(_.module.msiio <> msiio)
80    axi_reg_imsic.foreach(_.module.msiio <> msiio)
81    msi.foreach(_ <> msiio)
82  }
83
84  lazy val module = new imsic_bus_top_imp(this)
85}
86