fix(trace): fix parameters of trace (#4561)

feat(AIA): integrate ChiselAIA again (#4509)

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XS

feat(Top): make address spaces of seperate TL port configurable (#4496)

- `SeperateTLBus` and `SeperateTLBusRanges`: Generate a separate
TileLink bus with corresponding address ranges
- with `XSNoCTopConfig`: Multiple ranges can be specified, and
`SeperateDM` is ignored
- without `XSNoCTopConfig`: exactly one address range can be specified,
and can only be used to connected with DM by `SeperateDM`

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Revert "feat(AIA): integrate ChiselAIA (#4378)" (#4429)

This reverts commit 7fbc1cb42a2c96ef89a1dfd0f5f885ccada40c26.

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoo

feat(XSNoCTop): Power down and WFI gating (#4373)

The low-power features include the following:
* when Core is in WFI state, Core+L2 clock is gated and restore clocks
only when interrupt/reset/snoop.
* low-power process is controlled by FSM to follow the steps: flush L2
-> core enter WFI state -> send power-down request to SoC (o_cpu_no_op)
* SoC plays as PPU to generate power on/off sequence with signals:
isolation/reset/clock, also the power on/off req/ack signals

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feat(AIA): integrate ChiselAIA (#4378)

config: add fpga diff top on tilelink for diff_top (#4370)

In order to be compatible with st's environment, the fpga difftest
project in tilelink is generated in the same way as noc top, which leads

config: add fpga diff top on tilelink for diff_top (#4370)

In order to be compatible with st's environment, the fpga difftest
project in tilelink is generated in the same way as noc top, which leads
tilelink top and difftest signals to difftop together.

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feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
inc

feat: support seperate DebugModule TileLink bus (#4299)

This commit supports a configurable extra TileLink bus for DebugModule
besides the peripheral device bus. This involves all 3 environments
including TileLink-XSTop, CHI-XSTop, CHI-XSNoCTop. The feature is
disabled by default. To enable it, you can add `SEPERATE_DM_BUS=1` in
the make command line.

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feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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fix(Soc, CoupledL2): correct port width of CHI Issue C (#4290)

fix(SoC, OpenNCB): add support for CHI issue C (#4281)

Co-authored-by: Kumonda221 <[email protected]>

fix(Config): add the 'L3CacheCtrl' address space permission back (#4235)

feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/d

feat(XSNoCDiffTop): wrap XSNoCTop with Difftest Interface

To apply Difftest framework for CHI NoC, we wrapper lazy XSNoCTop
inside XSNoCDiffTop when difftest enabled, and expose necessary
soc/core/difftest IOs.

Currently we use two-step flow for CHI-NoC-XS as follow:
Step1. Generate single-core XSNoCDiffTop with JsonProfile,
which support generate another DifftestEndpoint seperately.
Step2. Generate n-core Difftest according to JsonProfile
Step3. Connect XS and Difftest manually or by some scripts.

As XSNoCDiffTop is only part of Difftest, we collect PerfCounters
for each DiffTop, need control signals passed from Outer module.
And to avoid potential connection problem, we add checker module
and CI test.

To maintain compatibility with previous IT/ST flow, we extend
XSNoCDiffTopConfig to enable difftest wrapper.

An example usage:
make verilog PLDM=1 PLDM_ARGS="--difftest-config H" CONFIG=XSNoCDiffTopConfig

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fix(Configs): set L3CacheParam or OpenLLCParam by EnableCHI (#4185)

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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fix(DM, SBA): add `TLWidthWidget` for sysbus

fix(trace): fix width of iaddr

feat(trace): add TraceCoreInterface in top.

fix: change CHIAsyncQueueBridge depth to 16 (#3768)

To support maximum number of L-Credits defined in CHI.IssueE.b.14.2.1

feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)

* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and O

feat(SoC): Replace DummyLLC with OpenLLC+OpenNCB in KunminghuV2Config (#3672)

* Bump OpenLLC to introduce the CHI-to-AXI bridge `OpenNCB`
* Build the SoC under KunminghuV2Config using OpenNCB and OpenLLC
* Update build dependencies and submodule initialization rules

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fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the

fix(MMIO): use fine-grained on-chip MMIO ranges (#3730)

Previously, on-chip devices use a continuous memory range, which
contains many memory holes not actually used. If we access these holes,
the core will hang. This commit use fine-grained on-chip MMIO ranges so
that memory accessing of these holes will be routed out of core and
handled by other mechanisms.

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refactor(Pmem): use `Seq` for physical memory ranges (#3622)

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

feat(Synchronizer): use unified AsyncResetSynchronizerShiftReg (#3609)

SoC, XSNoCTop, XSTileWrap: add switch for the async bridges (#3459)