| #
279a83c2 |
| 20-Jan-2021 |
Allen <[email protected]> |
Use DontCare to remove L2 inner A channel's data field.
This effectly reduces the number of bus data wires from 256 * 3 to 256 * 2.
Use DataDontCareNode to add DontCare to the tilelink nodes you are
Use DontCare to remove L2 inner A channel's data field.
This effectly reduces the number of bus data wires from 256 * 3 to 256 * 2.
Use DataDontCareNode to add DontCare to the tilelink nodes you are
interested in.
show more ...
|
| #
ae1373cb |
| 18-Jan-2021 |
zhanglinjuan <[email protected]> |
SoC/XSCore/L2Prefetcher: Connect BestOffsetPrefetch train req from L2
|
| #
13acf83a |
| 17-Jan-2021 |
jinyue110 <[email protected]> |
icache: add icache uncache support
|
| #
367512b7 |
| 17-Jan-2021 |
jinyue110 <[email protected]> |
Merge branch 'master' into icache-uncache
|
| #
97eae8a0 |
| 10-Jan-2021 |
Wang Huizhe <[email protected]> |
l3cache,multi-bank: enable banking in normal ways
1. duplicated connection to cache node enables banking
2. properly place filter node in manager side
(then InclusiveCahce can fix the banked addres
l3cache,multi-bank: enable banking in normal ways
1. duplicated connection to cache node enables banking
2. properly place filter node in manager side
(then InclusiveCahce can fix the banked address)
3. use out-of-box bankbinder utility
show more ...
|
| #
737d2306 |
| 12-Jan-2021 |
Wang Huizhe <[email protected]> |
L3,bank: modify address to avoid dead setBits
|
| #
7fc10034 |
| 12-Jan-2021 |
zhanglinjuan <[email protected]> |
Merge branch 'master' into dev-prefetcher
|
| #
a7e191f2 |
| 12-Jan-2021 |
Yinan Xu <[email protected]> |
Merge branch 'opt-load-miss-fix' into putDCacheAndUnCacheIntoMemBlock
|
| #
cb9302fe |
| 11-Jan-2021 |
zhanglinjuan <[email protected]> |
Merge branch 'master' into dev-prefetcher
|
| #
189e7a33 |
| 11-Jan-2021 |
zhanglinjuan <[email protected]> |
SoC/L2Prefetcher: add L2Prefetcher using tilelink
|
| #
0cff4510 |
| 11-Jan-2021 |
Allen <[email protected]> |
MemBlock: put dcache and uncache into MemBlock.
|
| #
4a26299e |
| 08-Jan-2021 |
wangkaifan <[email protected]> |
plic: finish plic connection to SoC
* urge tests for external interrupt
|
| #
2a37122e |
| 08-Jan-2021 |
wangkaifan <[email protected]> |
top: extend meip for dualcore
|
| #
0668d426 |
| 07-Jan-2021 |
wangkaifan <[email protected]> |
clint: support dual-core clint
|
| #
6059ce48 |
| 01-Dec-2020 |
jinyue110 <[email protected]> |
Merge branch 'master' into icache-uncache
|
| #
5d65f258 |
| 01-Dec-2020 |
Yinan Xu <[email protected]> |
SoC: move l2cache to SoC
|
| #
1e1cfa36 |
| 17-Nov-2020 |
Allen <[email protected]> |
XSSoC: do not let AXI4 signals optimized out.
|
| #
be5d77a1 |
| 17-Nov-2020 |
Allen <[email protected]> |
XSSoC: MMIO bus uses AXI4.
|
| #
f874f036 |
| 14-Nov-2020 |
Yinan Xu <[email protected]> |
xssim: add dual-core config
|
| #
8825f7bf |
| 14-Nov-2020 |
Yinan Xu <[email protected]> |
xscore: move dma to soc
|
| #
6e91caca |
| 14-Nov-2020 |
Yinan Xu <[email protected]> |
soc: move l3 outside core
|
| #
d709d2f8 |
| 11-Nov-2020 |
Allen <[email protected]> |
XSCore: XSCore access memory with 4 AXI4 channels.
Now, they are still 64bit(negotiated by diplomacy), since AXI4RAM is 64bit wide.
Considering changing AXI4RAM to 64bit.
|
| #
35bfeecb |
| 02-Nov-2020 |
Yinan Xu <[email protected]> |
csr: use IO for mtip,msip,meip
|
| #
799b61e0 |
| 12-Sep-2020 |
LinJiawei <[email protected]> |
TLTimer: impl msip, fix mtip's connection bug
|
| #
1865a66f |
| 19-Aug-2020 |
linjiawei <[email protected]> |
XSSim: Insert a buffer at mmio pass to avoid dead lock
|