rewrite core with diplomacy

diplomacy soc finish, use dummy core now

MMIOTLToAXI4: add a TL to AXI4 converter for MMIO.

SOC: move to tilelink, remove simple bus

Merge master into dev-fronend

SoC: use larger MMIO space to access frame buffer

soc: disable l2cache and l2prefetch

Adapt device address

Initial Commit of XiangShan CPU

Use fake Icache to fetch 8 instructions per cycle.

system,SoC; enable ILA

system,SoC: clean up external CLINT

system,SoC: move CLINT into SoC

Merge branch 'master' into merge-master

Merge branch 'master' into prefetch

Merge branch 'merge-master' into dev-linux-tlb

add prefetcher into l2cache

noop,top: support frontend slave ports

fix indent

refactor some code

fix indent

system,SoC: now L2 cache works well

system,SoC: define L2 relative parameter, still buggy

* microbench test fails even L2 is disabled

Merge branch 'master' into l2cache

fix bugs in l2cache(turn off prefetcher)

nothing