| #
83cb791f |
| 02-Apr-2021 |
allen <[email protected]> |
L2/L3: support configurable uncached get and let L3 cache GET (#722)
* Fixed perf counter does not print bug in BlockInclusiveCache.
* BlockInclusiveCache: Dont Probe L1 On Hint Hit.
* L2 use
L2/L3: support configurable uncached get and let L3 cache GET (#722)
* Fixed perf counter does not print bug in BlockInclusiveCache.
* BlockInclusiveCache: Dont Probe L1 On Hint Hit.
* L2 use UncachedGet, L3 cache Get.
* Bump L2
Co-authored-by: LinJiawei <[email protected]>
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|
| #
5c5bd416 |
| 30-Mar-2021 |
ljw <[email protected]> |
LogUtils: remove trait 'HasXSLog' (#732)
|
| #
9d0addb2 |
| 27-Mar-2021 |
ljw <[email protected]> |
L2/L3: set replacement policy to plru (#718)
* L2/L3: set replacement policy to plru
* Bump l2
|
| #
c17003d2 |
| 26-Mar-2021 |
Allen <[email protected]> |
Merge branch 'master' of github.com:RISCVERS/XiangShan
|
| #
11b3c588 |
| 26-Mar-2021 |
Allen <[email protected]> |
Pass enablePerf to BlockInclusiveCache.
L2 and L3 Only enablePerf when XSCore enables perf.
|
| #
4e3ce935 |
| 22-Mar-2021 |
ljw <[email protected]> |
Beu: separate l1plus and icache (#705)
|
| #
2e3a956e |
| 19-Mar-2021 |
LinJiawei <[email protected]> |
Top: add beu
|
| #
953a0310 |
| 19-Mar-2021 |
LinJiawei <[email protected]> |
Soc: insert a buffer between L3 and dram
|
| #
9637c0c6 |
| 18-Mar-2021 |
LinJiawei <[email protected]> |
Soc: connect beu and cores
|
| #
0584d3a8 |
| 18-Mar-2021 |
LinJiawei <[email protected]> |
Soc: add bus error unit
|
| #
92a86cc7 |
| 05-Mar-2021 |
ljw <[email protected]> |
Remove regs and logic gates in top module (#642)
* xscore: remove reg and logic in xscore top module
* XSCore: remove logic in top module
* Fp/Int block: fix write back bug
Co-authored-by:
Remove regs and logic gates in top module (#642)
* xscore: remove reg and logic in xscore top module
* XSCore: remove logic in top module
* Fp/Int block: fix write back bug
Co-authored-by: Yinan Xu <[email protected]>
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|
| #
21377543 |
| 24-Feb-2021 |
zhanglinjuan <[email protected]> |
L2Prefetcher: specify addressBits for PrefetcherIO
|
| #
87b0fcb0 |
| 24-Feb-2021 |
zhanglinjuan <[email protected]> |
XSSoc/L2Prefetcher: move l2 prefetcher from XSCore to SoC
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| #
7a77cff2 |
| 23-Feb-2021 |
Yinan Xu <[email protected]> |
csr: pass hartId by IO to dedup CSRs for different XSCores
|
| #
ce14a4f1 |
| 09-Feb-2021 |
wangkaifan <[email protected]> |
Merge branch 'dual-dev' into dual-dev-clean
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| #
3d499721 |
| 09-Feb-2021 |
wangkaifan <[email protected]> |
difftest: eliminate original difftest framework
|
| #
84eb3d54 |
| 04-Feb-2021 |
Yinan Xu <[email protected]> |
soc: set the number of external interrupts to 150 and dontTouch it
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| #
5f00f642 |
| 28-Jan-2021 |
wangkaifan <[email protected]> |
difftest: able to show trap info for dual-core
|
| #
9df735b7 |
| 25-Jan-2021 |
wangkaifan <[email protected]> |
Merge branch 'master' into dual-stable
|
| #
a165bd69 |
| 25-Jan-2021 |
wangkaifan <[email protected]> |
difftest: support dual-core difftest signal in-core
* should be compatible with single core difftest framework
|
| #
1837e787 |
| 22-Jan-2021 |
Yinan Xu <[email protected]> |
Merge pull request #480 from RISCVERS/changeL2L3SRAMWidth
L2, L3: change SRAM width to 256 bit.
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| #
8d9f4ff7 |
| 22-Jan-2021 |
Allen <[email protected]> |
L2, L3: change SRAM width to 256 bit.
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| #
b6d47149 |
| 22-Jan-2021 |
zhanglinjuan <[email protected]> |
Merge branch 'master' into dev-prefetcher
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| #
283d1da7 |
| 21-Jan-2021 |
jinyue110 <[email protected]> |
Merge branch 'master' into icache-uncache
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| #
220f98bb |
| 21-Jan-2021 |
jinyue110 <[email protected]> |
Move Instruction uncache into frontend
|