add performance counters at core and hauncun (#1156)

* Add perf counters
* add reg from hpm counter source
* add print perfcounter enable

rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 regi

rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

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core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

dispatch2Rs: load balance between two ports (#1110)

This commit adds load balance support for two dispatch ports, between 0
and 2, 1 and 3, etc.

renameTable: optimize read and write timing (#1101)

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at d

renameTable: optimize read and write timing (#1101)

This commit optimizes RenameTable's timing.

Read addresses come from instruction buffer directly and has best
timing. So we let data read at decode stage and bypass write data
from this clock cycle to the read data at next cycle.

For write, we latch the write request and process it at the next cycle.

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Add runahead debug signals (#1082)

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does no

Add runahead debug signals (#1082)

* runahead: add runahead support (WIP)

* runahead: fix redirect event

* difftest: bump difftest

* runahead: bump version

Note: current runahead does not support instruction fusion, disable that
in XiangShan if runahead is needed

* runahead: bump version

* difftest: bump version to support runahead

* chore: bump huancun to make ci happy

* chore: fix wrong submodule url

* difftest: bump version

BREAKING CHANGE: nemu update_config api has changed

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core: update parameters and module organizations (#1080)

This commit moves load/store reservation stations into the first
ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module
is

core: update parameters and module organizations (#1080)

This commit moves load/store reservation stations into the first
ExuBlock (or calling it IntegerBlock). The unnecessary dispatch module
is also removed from CtrlBlock.

Now the module organization becomes:
* ExuBlock: Int RS, Load/Store RS, Int RF, Int FUs
* ExuBlock_1: Fp RS, Fp RF, Fp FUs
* MemBlock: Load/Store FUs

Besides, load queue has 80 entries and store queue has 64 entries now.

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misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We

core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

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backend: clean up exception vector usages (#1026)

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, in

backend: clean up exception vector usages (#1026)

This commit cleans up exception vector usages in backend.

Previously the exception vector will go through the pipeline with the
uop. However, instructions with exceptions will enter ROB when they are
dispatched. Thus, actually we don't need the exception vector when an
instruction enters a function unit.

* exceptionVec, flushPipe, replayInst are reset when an instruction
enters function units.

* For execution units that don't have exceptions, we reset their output
exception vectors to avoid ROB to record them.

* Move replayInst to CtrlSignals.

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chore: fix frontend / memblock merge conflict

Merge branch 'master' into vaddr-fwd

frontend: code clean ups

Merge remote-tracking branch 'origin/master' into vaddr-fwd

Merge branch 'master' into dcp-merge-master

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

*

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

* build.sc: add testOne method for unit test

* AdderTest: add testbench for Adder (passed)

* AdderTree: Add testbench for AdderTree (passed)

* ReferenceCounter: implement a 2-bit counter

* Rename: remove redundant code

* Rename: prepared for move elimination [WIP]

* Roq: add eliminated move bit in roq entry;
label elim move inst as writebacked
AlternativeFreeList: new impl for int free list
Rename: change io of free list
Dispatch1: (todo) not send move to intDq
Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio
ReferenceCounter: add debug print msg

* Dispatch1: [BUG FIX] not send move inst to IntDq

* DecodeUnit: [BUG FIX] differentiate li from mv

* Bug fix:
1. Dispatch1: should not label pdest of move as busy in busy table
2. Rename: use psrc0 to index bit vec isMax
3. AlternativeFreeList: fix maxVec calculation logic and ref counter
increment logic
Besides, more debug info and assertions were added.

* AlternativeFreeList Bug Fix:
1. add redirect input - shouldn't allocate reg when redirect is
valid
2. handle duplicate preg in roqCommits in int free list

* AlternativeFreeList: Fix value assignment race condition

* Rename: Fix value assignment race condition too

* RenameTable: refactor spec/arch table write process

* Roq: Fix debug_exuData of move(addi) instruction
(it was trash data before because move needn't enter exu)

* Rename: change intFreeList's redirect process
(by setting headPtr back) and flush process

* ME: microbench & coremark & linux-hello passed
1. DecodeUnit: treat `mv x,x` inst as non-move
2. AlternativeFreeList: handle duplicate walk req correctly
3. Roq: fix debug_exuData bug (make sure writeback that updates
debug_exuData happens before ME instruction in program order)

* AlternativeFreeList: License added
build.sc: remove unused config
Others: comments added

* package rename: remove unused modules

* Roq: Replace debug_prf with a cleaner fix method

* Disp1/AltFL/Rename: del unnecessary white spaces

* build.sc: change stack size
AlternativeFreeList: turn off assertions

* build.sc: change stack size for test

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ftq, ctrlblock: code clean ups

mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is gene

mem: loadpipe will not miss if fullForward succeed

New option `EnableFastForward` is added to config list.
EnableFastForward will reduce L1D$ miss but make timing worse.

* `forwardMaskFast` is generated at load_s1, it is used to generate
fastUop for fast wakeup
* `forwardMask` is generated at load_s2, it will be used to check if
forward result is correct

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core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support

core: add basic debug mode features (#918)

Basic features of debug mode are implemented.

* Rewrite CSR for debug mode
* Peripheral work for implementing debug module
* Added single step support
* Use difftest with JTAG support

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Merge branch 'decoupled-frontend-ifu' into decoupled-frontend

ctrlblock: remove redirect_cfiUpdate port, and use stage3Redirect

rob: support replay inst from rob

Merge branch 'master' into merge-master

ftq, ctrlblock: now ctrlblock only read pc and target from ftq,
br_hit and hist is read at ftq when redirect is sent to bpu

bpu: Add Tage

Add Tage into Composer
Add global history manage logic in BPU
Modify CfiUpdate interface: sawNotTakenBranch -> br_hit