feat(Difftest): add multi-core vector load check (#4361)

Currently, we implement the multi core vector load check in difftest.
We modified difftest and NEMU and added related content in XiangShan.

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

show more ...

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

show more ...

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbite

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbiter
wbtorob:
fix writebacknum count: delete extra count for exu which cannot be compressed

show more ...

WbDataPath: support v0 & vl split

Merge branch 'master' into vlsu-merge-master-0504

Utility: Fix wrong use case of XSError in XiangShan

Some XSError message uses `s` to format strings with some information
peeked from the circuit. It does not peek the correct information from RTL
a

Utility: Fix wrong use case of XSError in XiangShan

Some XSError message uses `s` to format strings with some information
peeked from the circuit. It does not peek the correct information from RTL
and makes the module itself fail to dedup. This commit fixes this by
replacing `s` with `p`.

Signed-off-by: Yangyu Chen <[email protected]>

show more ...

Merge branch 'master' into vlsu-merge-master-0504

Backend: add FpScheduler

VLSU: support more than one vlsu feedback & writeback

More issuequeues need to be added to use more lsu pipelines

WbDataPath: add 1 cycle delay when vf exe units write back to int regfile

WbDataPath: better signal connection in WbDataPath

WbDataPath: add 1 cycle delay when vf exe units write back to int regfile

WbDataPath: better signal connection in WbDataPath

Backend: remove unused extra RF read ports, connect real commit vtype to VTypeGen

WbDataPath: add RealWBArbiter for WbDataPath

Parameters: remove write port configs for store

WbDataPath: use new WBArbiter

backend: implement uncertain latency exeUnit WbArbiter

backend,param: merge vldu and vstu into one exu

backend,param: merge vldu and vstu into one exu

fix compile error

Backend: WBDataPath and ROB support vlsu(vld res merge and exceptionGen)

fix difftest connection error

fix merge error