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ca0aa835 |
| 28-Sep-2024 |
Xuan Hu <[email protected]> |
feat(CSR): add No.16,18 and 19 exceptions (#3640)
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| #
bfac3305 |
| 19-Jul-2024 |
peixiaokun <[email protected]> |
CSR, RVH: fix the wrong stval and htval when igpf happens
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| #
f60da58c |
| 09-Jun-2024 |
Xuan Hu <[email protected]> |
NewCSR: set GVA=1 when hls insts trap load/store exceptions
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| #
ab449222 |
| 20-May-2024 |
sinceforYy <[email protected]> |
NewCSR: initialize machine level interrupt-related CSR
* Initialize mip, mie, mideleg, medeleg CSR to 0
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| #
039cdc35 |
| 08-Mar-2024 |
Xuan Hu <[email protected]> |
NewCSR: modulized implementation
NewCSR: add Hypervisor CSRs
NewCSR: optimize dump fields using chisel3.reflect.DataMirror
NewCSR: add VirtualSupervisor CSRs
NewCSR: refactor VirtualSupervisor an
NewCSR: modulized implementation
NewCSR: add Hypervisor CSRs
NewCSR: optimize dump fields using chisel3.reflect.DataMirror
NewCSR: add VirtualSupervisor CSRs
NewCSR: refactor VirtualSupervisor and Hypervisor CSRs
* Make sure ValidIO etc function return CSREnumType not EnumType
* TODO: AIA for vs
NewCSR: add MachineLevel CSRs
NewCSR: fix alias relationship between hip, hvip and vsip
NewCSR: add SupervisorLevel CSRs
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