Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

backend,vector: fix vector relative bug and first vadd instr success

Modification and Bugs includes:
1. readFpRf/writeFpRf is replaced with readFpVecRf/writeFpVecRf in some
places;
2. fpWen is repla

backend,vector: fix vector relative bug and first vadd instr success

Modification and Bugs includes:
1. readFpRf/writeFpRf is replaced with readFpVecRf/writeFpVecRf in some
places;
2. fpWen is replaced with fpVecWen in some places;
3. add ADD/SUB decode info
4. dispatch logic modification
5. dataWidth & wakeup logic in rs
6. ExuInput/ExuOutput at many places
7. fuSel inside FUBlock of FMAC
8. FuType encoding
9. many other bugs

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

backend,RS: rewrite RS to optimize timing (#812)

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more

backend,RS: rewrite RS to optimize timing (#812)

* test,vcs: call $finish when difftest fails

* backend,RS: refactor with more submodules

This commit rewrites the reservation station in a more configurable style.

The new RS has not finished.
- Support only integer instructions
- Feedback from load/store instructions is not supported
- Fast wakeup for multi-cycle instructions is not supported
- Submodules are refined later

* RS: use wakeup signals from arbiter.out

* RS: support feedback and re-schedule when needed

For load and store reservation stations, the instructions that left RS before may be
replayed later.

* test,vcs: check difftest_state and return on nemu trap instructions

* backend,RS: support floating-point operands and delayed regfile read for store RS

This commit adds support for floating-point instructions in reservation stations.
Beside, currently fp data for store operands come a cycle later than int data. This
feature is also supported.

Currently the RS should be ready for any circumstances.

* rs,status: don't trigger assertions when !status.valid

* test,vcs: add +workload option to specify the ram init file

* backend,rs: don't enqueue when redirect.valid or flush.valid

* backend,rs: support wait bit that instruction waits until store issues

This commit adds support for wait bit, which is mainly used in load and
store reservation stations to delay instruction issue until the corresponding
store instruction issued.

* backend,RS: optimize timing

This commit optimizes BypassNetwork and PayloadArray timing.

- duplicate bypass mask to avoid too many FO4
- use one-hot vec to get read data

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