1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.issue 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import utility._ 25 26class WakeupQueue(number: Int)(implicit p: Parameters) extends XSModule { 27 val io = IO(new Bundle { 28 val in = Flipped(ValidIO(new MicroOp)) 29 val out = ValidIO(new MicroOp) 30 val redirect = Flipped(ValidIO(new Redirect)) 31 }) 32 if (number < 0) { 33 io.out.valid := false.B 34 io.out.bits := DontCare 35 } else if(number == 0) { 36 io.in <> io.out 37 io.out.valid := io.in.valid 38 // NOTE: no delay bypass don't care redirect 39 } else { 40 val queue = Seq.fill(number)(RegInit(0.U.asTypeOf(new Bundle{ 41 val valid = Bool() 42 val bits = new MicroOp 43 }))) 44 queue(0).valid := io.in.valid && !io.in.bits.robIdx.needFlush(io.redirect) 45 queue(0).bits := io.in.bits 46 (0 until (number-1)).map{i => 47 queue(i+1) := queue(i) 48 queue(i+1).valid := queue(i).valid && !queue(i).bits.robIdx.needFlush(io.redirect) 49 } 50 io.out.valid := queue(number-1).valid 51 io.out.bits := queue(number-1).bits 52 for (i <- 0 until number) { 53 XSDebug(queue(i).valid, p"BPQue(${i.U}): pc:${Hexadecimal(queue(i).bits.cf.pc)} robIdx:${queue(i).bits.robIdx}" + 54 p" pdest:${queue(i).bits.pdest} rfWen:${queue(i).bits.ctrl.rfWen} fpWen:${queue(i).bits.ctrl.fpWen} vecWen:${queue(i).bits.ctrl.vecWen}\n") 55 } 56 } 57} 58