| #
c01e75b5 |
| 16-Apr-2025 |
Ziyue Zhang <[email protected]> |
fix(exceptionGen): clear isEnqExcp when older or curr wb exception coming (#4570)
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| #
ec6936cb |
| 24-Oct-2024 |
Xuan Hu <[email protected]> |
fix(VecExcp): isEnqExcp should be set 0 when writeback has older exception (#3778)
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| #
11bd888f |
| 17-Oct-2024 |
Xuan Hu <[email protected]> |
fix(VecExcp): use `isEnqExcp` to distinguish pc and mem trigger (#3755)
Futher fix after #3722.
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| #
19870d35 |
| 12-Oct-2024 |
Xuan Hu <[email protected]> |
fix(ExceptionGen): assign vector exception info when robidxes equal (#3714)
* Trigger action also update with the smaller vstart uop.
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| #
a8c570da |
| 29-Sep-2024 |
Anzooooo <[email protected]> |
fix(Exceptiongen): fix exceptionVec generation logic
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| #
c0355297 |
| 11-Sep-2024 |
Anzooooo <[email protected]> |
feat(VLSU): set vstart when the support vector accesses anomalies
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| #
7e0f64b0 |
| 21-Aug-2024 |
Guanghui Cheng <[email protected]> |
Trigger: refactor trigger information in pipeline. (#3403)
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| #
3e8a0170 |
| 25-Jul-2024 |
Xuan Hu <[email protected]> |
ROB: clear flushPipe when the enq uop has exception (#3281)
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| #
985804e6 |
| 10-May-2024 |
Xuan Hu <[email protected]> |
Backend: split vector load/store FuType by is segment or not
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| #
780712aa |
| 19-Mar-2024 |
xiaofeibao-xjtu <[email protected]> |
backend: new rob 8 banks read and 8 commit width
|