xref: /XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala (revision c01e75b55fbe706c21954429f2ec968cbc61a2cc) 
1/***************************************************************************************
2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3 * Copyright (c) 2020-2021 Peng Cheng Laboratory
4 *
5 * XiangShan is licensed under Mulan PSL v2.
6 * You can use this software according to the terms and conditions of the Mulan PSL v2.
7 * You may obtain a copy of Mulan PSL v2 at:
8 *          http://license.coscl.org.cn/MulanPSL2
9 *
10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13 *
14 * See the Mulan PSL v2 for more details.
15 ***************************************************************************************/
16
17package xiangshan.backend.rob
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import difftest._
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utility._
25import utils._
26import xiangshan._
27import xiangshan.backend.BackendParams
28import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
29import xiangshan.backend.fu.{FuConfig, FuType}
30import xiangshan.frontend.FtqPtr
31import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr}
32import xiangshan.backend.Bundles.{DynInst, ExceptionInfo, ExuOutput}
33import xiangshan.backend.ctrlblock.{DebugLSIO, DebugLsInfo, LsTopdownInfo}
34import xiangshan.backend.fu.vector.Bundles.VType
35import xiangshan.backend.rename.SnapshotGenerator
36
37class ExceptionGen(params: BackendParams)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
38  val io = IO(new Bundle {
39    val redirect = Input(Valid(new Redirect))
40    val flush = Input(Bool())
41    val enq = Vec(RenameWidth, Flipped(ValidIO(new RobExceptionInfo)))
42    // csr + load + store + varith + vload + vstore
43    val wb = Vec(params.numException, Flipped(ValidIO(new RobExceptionInfo)))
44    val out = ValidIO(new RobExceptionInfo)
45    val state = ValidIO(new RobExceptionInfo)
46  })
47
48  val wbExuParams = params.allExuParams.filter(_.exceptionOut.nonEmpty)
49
50  def getOldest(valid: Seq[Bool], bits: Seq[RobExceptionInfo]): RobExceptionInfo = {
51    def getOldest_recursion(valid: Seq[Bool], bits: Seq[RobExceptionInfo]): (Seq[Bool], Seq[RobExceptionInfo]) = {
52      assert(valid.length == bits.length)
53      if (valid.length == 1) {
54        (valid, bits)
55      } else if (valid.length == 2) {
56        val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0)))))
57        for (i <- res.indices) {
58          res(i).valid := valid(i)
59          res(i).bits := bits(i)
60        }
61        val oldest = Mux(
62          !valid(1) || (valid(0) && (isAfter(bits(1).robIdx, bits(0).robIdx) || ((bits(1).robIdx === bits(0).robIdx) && bits(1).vuopIdx > bits(0).vuopIdx))),
63          res(0),
64          res(1)
65        )
66        (Seq(oldest.valid), Seq(oldest.bits))
67      } else {
68        val left = getOldest_recursion(valid.take(valid.length / 2), bits.take(valid.length / 2))
69        val right = getOldest_recursion(valid.drop(valid.length / 2), bits.drop(valid.length / 2))
70        getOldest_recursion(left._1 ++ right._1, left._2 ++ right._2)
71      }
72    }
73    getOldest_recursion(valid, bits)._2.head
74  }
75
76
77  val currentValid = RegInit(false.B)
78  val current = Reg(new RobExceptionInfo)
79
80  // orR the exceptionVec
81  val lastCycleFlush = RegNext(io.flush)
82  val enq_s0_valid = VecInit(io.enq.map(e => e.valid && e.bits.has_exception && !lastCycleFlush))
83  val enq_s0_bits = WireInit(VecInit(io.enq.map(_.bits)))
84  enq_s0_bits zip io.enq foreach { case (sink, source) =>
85    sink.flushPipe := source.bits.flushPipe && !source.bits.hasException
86  }
87
88  // s0: compare wb in 6 groups
89  val csr_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.filter(t => t.isCsr).nonEmpty).map(_._1)
90  val load_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.filter(_.fuType == FuType.ldu).nonEmpty).map(_._1)
91  val store_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.filter(t => t.isSta || t.fuType == FuType.mou).nonEmpty).map(_._1)
92  val varith_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.filter(_.isVecArith).nonEmpty).map(_._1)
93  val vls_wb = io.wb.zip(wbExuParams).filter(_._2.fuConfigs.exists(x => FuType.FuTypeOrR(x.fuType, FuType.vecMem))).map(_._1)
94
95  val writebacks = Seq(csr_wb, load_wb, store_wb, varith_wb, vls_wb)
96  val in_wb_valids = writebacks.map(_.map(w => w.valid && w.bits.has_exception && !lastCycleFlush))
97  val wb_valid = in_wb_valids.zip(writebacks).map { case (valid, wb) =>
98    valid.zip(wb.map(_.bits)).map { case (v, bits) => v && !(bits.robIdx.needFlush(io.redirect) || io.flush) }.reduce(_ || _)
99  }
100  val wb_bits = in_wb_valids.zip(writebacks).map { case (valid, wb) => getOldest(valid, wb.map(_.bits))}
101
102  val s0_out_valid = wb_valid.map(x => RegNext(x))
103  val s0_out_bits = wb_bits.zip(wb_valid).map{ case(b, v) => RegEnable(b, v)}
104
105  // s1: compare last six and current flush
106  val s1_valid = VecInit(s0_out_valid.zip(s0_out_bits).map{ case (v, b) => v && !(b.robIdx.needFlush(io.redirect) || io.flush) })
107  val s1_out_bits = RegEnable(getOldest(s0_out_valid, s0_out_bits), s1_valid.asUInt.orR)
108  val s1_out_valid = RegNext(s1_valid.asUInt.orR)
109
110  val enq_s1_valid = RegNext(enq_s0_valid.asUInt.orR && !io.redirect.valid && !io.flush)
111  val enq_s1_bits: RobExceptionInfo = RegEnable(ParallelPriorityMux(enq_s0_valid, enq_s0_bits), enq_s0_valid.asUInt.orR && !io.redirect.valid && !io.flush)
112
113  // s2: compare the input exception with the current one
114  // priorities:
115  // (1) system reset
116  // (2) current is valid: flush, remain, merge, update
117  // (3) current is not valid: s1 or enq
118  val current_flush = current.robIdx.needFlush(io.redirect) || io.flush
119  val s1_flush = s1_out_bits.robIdx.needFlush(io.redirect) || io.flush
120
121  val isVecUpdate = s1_out_bits.vstart < current.vstart || !current.vstartEn
122  when (currentValid) {
123    when (current_flush) {
124      currentValid := Mux(s1_flush, false.B, s1_out_valid)
125    }
126    when (s1_out_valid && !s1_flush) {
127      when (isAfter(current.robIdx, s1_out_bits.robIdx)) {
128        current := s1_out_bits
129        // s1 is older than current and caused by wb, set current.isEnqExcp to false
130        current.isEnqExcp := false.B
131      }.elsewhen (current.robIdx === s1_out_bits.robIdx) {
132        current.exceptionVec := Mux(isVecUpdate, s1_out_bits.exceptionVec, current.exceptionVec)
133        current.hasException := Mux(isVecUpdate, s1_out_bits.hasException, current.hasException)
134        current.flushPipe := (s1_out_bits.flushPipe || current.flushPipe) && !s1_out_bits.exceptionVec.asUInt.orR
135        current.replayInst := s1_out_bits.replayInst || current.replayInst
136        current.singleStep := s1_out_bits.singleStep || current.singleStep
137        current.trigger   := Mux(isVecUpdate, s1_out_bits.trigger,    current.trigger)
138        current.vstart    := Mux(isVecUpdate, s1_out_bits.vstart,     current.vstart)
139        current.vstartEn  := Mux(isVecUpdate, s1_out_bits.vstartEn,   current.vstartEn)
140        current.isVecLoad := Mux(isVecUpdate, s1_out_bits.isVecLoad,  current.isVecLoad)
141        current.isVlm     := Mux(isVecUpdate, s1_out_bits.isVlm,      current.isVlm)
142        current.isStrided := Mux(isVecUpdate, s1_out_bits.isStrided,  current.isStrided)
143        current.isIndexed := Mux(isVecUpdate, s1_out_bits.isIndexed,  current.isIndexed)
144        current.isWhole   := Mux(isVecUpdate, s1_out_bits.isWhole,    current.isWhole)
145        current.nf        := Mux(isVecUpdate, s1_out_bits.nf,         current.nf)
146        current.vsew      := Mux(isVecUpdate, s1_out_bits.vsew,       current.vsew)
147        current.veew      := Mux(isVecUpdate, s1_out_bits.veew,       current.veew)
148        current.vlmul     := Mux(isVecUpdate, s1_out_bits.vlmul,      current.vlmul)
149        // current has a new exception caused by wb, set current.isEnqExcp to false
150        current.isEnqExcp := false.B
151      }
152    }
153  }.elsewhen (s1_out_valid && !s1_flush) {
154    currentValid := true.B
155    current := s1_out_bits
156    current.isEnqExcp := false.B
157  }.elsewhen (enq_s1_valid && !(io.redirect.valid || io.flush)) {
158    currentValid := true.B
159    current := enq_s1_bits
160    current.isEnqExcp := true.B
161  }
162
163  io.out.valid   := s1_out_valid || enq_s1_valid && enq_s1_bits.can_writeback
164  io.out.bits    := Mux(s1_out_valid, s1_out_bits, enq_s1_bits)
165  io.state.valid := currentValid
166  io.state.bits  := current
167
168}
169