timing(vecExcpMod): add pipe from rab and rat's signals

fix(rob): fix bug of canAcceptForDispatch

fix(VecExcp): commit vls exception after Rab commiting all reg pairs

fix(Rab): no need to limit diff commit valid only assert in commit state (#3760)

fix(ROB): vlsNeedCommit only assert one cycle to avoid dup message to RAB (#3702)

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merg

feat(VecLoad): add VecLoadExcp module to handle merging old/new data

* When NF not 0, the register indices are arranged group by group. But in exception handle progress, all registers needed to merge will be handled first, and then the registers needed to move will be handled later.
* The need merge vdIdx can be until 8, so 4 bits reg is needed.
* If the instruction is indexed, the eew of vd is sew from vtype. Otherwise, the eew of vd is encoded in instruction.
* Use ivemulNoLessThanM1 and dvemulNoLessThanM1 to produce vemul_i_d to avoid either demul or iemul is less than M1.
* For whole register load, need handle NF(nf + 1) dest regs.
* Use data EMUL to calculate number of dest reg.
* GetE8OffsetInVreg will return the n-th 8bit which idx mapped to.
* Since xs will flush pipe, when vstart is not 0 and execute vector mem inst, the value of vstart in CSR is the
first element of this vector instruction. When exception occurs, the vstart in writeback bundle is the new one,
So writebacked vstart should never be used as the beginning of vector mem operation.
* Non-seg indexed load use non-sequential vd.
* When "index emul" / "data emul" equals 2,
the old vd is located in vuopidx 0, 2, 4, 6,
the new vd is located in vuopidx 1, 3, 5, 7.
* Make rename's input not ready until VecExcpMod not busy.
* Delay trap passed to difftest until VecExcpMod not busy.
* Rab commit to VecExcpMod as it commit to Rat, and select real load reg maps in VecExcpMod.
* Use isDstMask to distinguish vlm and other vle.
* When isWhole, vd regs are sequential.

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fix(rab): parameterization of commit/walk num logic (#3618)

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

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timing(Rab): fix timing of state reg (#3517)

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbite

Backend fixtiming: fix rab/exuwb/wbtorob timing (#3032)

rab:
fix commit/walk/special walk Count from popcount to priority mux
exuwb:
fix exuwb Nto1 logic: add int/fp/vec 3 wbpath to wbarbiter
wbtorob:
fix writebacknum count: delete extra count for exu which cannot be compressed

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Rab: use Reg for debug

backend: new rob 8 banks read and 8 commit width

Backend: remove unused extra RF read ports, connect real commit vtype to VTypeGen

Backend: add clock gating to valid singal

Rab: shrink rab entry width

Rob: optimize timing, remove vconfig debugIO

Backend: disallow snapshot when there are tail uops at the same cycle

* When creating snapshot at the middle of split uops, RAT record the state before this snapshot, but ROB record the enqPtr conta

Backend: disallow snapshot when there are tail uops at the same cycle

* When creating snapshot at the middle of split uops, RAT record the state before this snapshot, but ROB record the enqPtr containing some states of last cycle.

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Rab: use `diffPtr` instead of `diffPtrOH` for better build speed

Rab: use snapshot enqueue condition of rob

Revert "Snapshot: fix enq condition"

This reverts commit a3ea5c1d41581cbff4cfc5175c0a4699c3786b0a.

Snapshot: fix enq condition

snapshot: flush conditionally when redirect comes

Rab: set io.canEnq to true immediately when state becomes idle

fix merge error

Rob: fix FP CSR issue when rob compressing