History log of /XiangShan/src/main/scala/xiangshan/frontend/Bim.scala (Results 26 – 50 of 64)
Revision Date Author Comments
# eedc2e58 26-Feb-2021 Steve Gou <[email protected]>

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and sbpctl address

* bpu: fix s3 connections

Co-authored-by: Yinan Xu <[email protected]>

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# 5420001e 23-Feb-2021 Lingrui98 <[email protected]>

ftq, bpu: add cycle on commit and redirect(for ras and loop


# 6f3fd419 17-Feb-2021 Lingrui98 <[email protected]>

ifu: merge srams with the same raddr


# 26549752 17-Feb-2021 Lingrui98 <[email protected]>

sram template: support multi-way write


# 58225d66 25-Jan-2021 LinJiawei <[email protected]>

Merge remote-tracking branch 'origin/master' into ftq


# ed9422c0 23-Jan-2021 Yinan Xu <[email protected]>

SRAMTemplate: fix wmask and update license


# 744c623c 22-Jan-2021 Lingrui98 <[email protected]>

ftq and all: now we can compile


# aff3da59 16-Jan-2021 LinJiawei <[email protected]>

add a desired name for each sram module


# 296ffc1d 07-Jan-2021 Lingrui98 <[email protected]>

core: enable rvc, bim: fix typo


# 8a97deb3 07-Jan-2021 Lingrui98 <[email protected]>

ifu, bpu: now we fetch with packet aligned pc


# 504ad047 04-Jan-2021 YikeZhou <[email protected]>

clean up deprecated decode codes


# bdbecbc1 28-Dec-2020 Lingrui98 <[email protected]>

bim: fix wrbypass bug


# 506320e5 19-Dec-2020 Lingrui98 <[email protected]>

bpu: add recover logic on replay for ras, prevent update on replay
for bim, btb, tage and ubtb


# a9c3d341 19-Dec-2020 Lingrui98 <[email protected]>

bpu: remove CFIUpdateInfoWithHist


# 43ad9482 19-Dec-2020 Lingrui98 <[email protected]>

change signal names related to brInfo


# fe3a74fc 18-Dec-2020 Yinan Xu <[email protected]>

BranchUpdateInfo: remove brTarget


# faa3595d 15-Dec-2020 Lingrui98 <[email protected]>

bim, btb, tage: rename signals with corresponding ifu stage


# e11e6a4c 07-Dec-2020 Lingrui98 <[email protected]>

ifu, bpu: try to improve ras timing, change ubtb and btb update logic


# 05f89604 03-Dec-2020 Lingrui98 <[email protected]>

ifu: use @chiselName annotation


# 4b17b4ee 03-Dec-2020 Lingrui98 <[email protected]>

ifu, bpu: now can run but got errors


# ceaf5e1f 01-Dec-2020 Lingrui98 <[email protected]>

frontend: half done refactoring


# 34ecc016 17-Nov-2020 Lingrui98 <[email protected]>

bim, lp: fix merge issues


# 7c65e95d 16-Nov-2020 Lingrui98 <[email protected]>

bim: get rid of BoringUtils


# b96b0ab7 09-Nov-2020 Lingrui98 <[email protected]>

bim: use LF for \n


# 89231490 11-Sep-2020 GouLingrui <[email protected]>

log clean ups


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