Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can est

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

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Beu: separate l1plus and icache (#705)

L1plusCache: add error io.

Perf: add more performance counter (#607)

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf s

Perf: add more performance counter (#607)

* perf: set acc arg of XSPerf as false by default

* perf: add write-port competition counter for intBlock & floatBlock

* perf: remove prefix of perf signal

* perf: add perf-cnt for interface between frontend & backend

* perf: modify perf-cnt for prefetchers

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Add a naive memory violation predictor (#591)

* WaitTable: add waittable framework

* WaitTable: get replay info from RedirectGenerator

* StoreQueue: maintain issuePtr for load rs

* RS: add

Add a naive memory violation predictor (#591)

* WaitTable: add waittable framework

* WaitTable: get replay info from RedirectGenerator

* StoreQueue: maintain issuePtr for load rs

* RS: add loadWait to rs (only for load Unit's rs)

* WaitTable: fix update logic

* StoreQueue: fix issuePtr update logic

* chore: set loadWaitBit in ibuffer

* StoreQueue: fix issuePtrExt update logic

Former logic does not work well with mmio logic

We may also make sure that issuePtrExt is not before cmtPtrExt

* WaitTable: write with priority

* StoreQueue: fix issuePtrExt update logic for mmio

* chore: fix typos

* CSR: add slvpredctrl

* slvpredctrl will control load violation predict micro architecture

* WaitTable: use xor folded pc to index waittable

Co-authored-by: ZhangZifei <[email protected]>

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csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and

csr,bpu: support enabling and disabling branch predictors via sbpctl (#593)

* csr: add sbpctrl to control branch predictors

* bpu: add dynamic switch to each predictor

* csr: change spfctl and sbpctl address

* bpu: fix s3 connections

Co-authored-by: Yinan Xu <[email protected]>

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csr: support prefetcher enable control via spfctl CSR

Merge remote-tracking branch 'origin/master' into ftq

ftq and all: now we can compile

Move Instruction uncache into frontend

icache: add icache uncache support

Frontend/IFU: place L1plusPrefetcher in Frontend

frontend: fix unconnected ifu ports

frontend: put icache and tlb into icache

change signal names related to brInfo

frontend: include icache

xscore: connect missing wires

XSCore: use Blocks

Merge branch 'master' into new-lbuf

Remove all boringutils except Regfile

Remove BoringUtils in fence unit

LoopBuffer: Separate the LoopBuffer and the IBuffer

LoopBuffer: Modify the interface to support configurability

Merge branch 'master' into dev-lbuf

LoopBuffer: Fix some bug