bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

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tage-sc: add bypassWrite for SC srams and fix a bug of resp_invalid_by_write in TageTable (#1702)

bpu: remove most reset signals of SRAMs

fix for chipsalliance/chisel3#2496 (#1563)

fix bugs of tage-sc (#1533)

* sc: fix a performance bug

* tage: fix number of use-alt-on-na counters

* tage: update provider u-bit according to provider results

bpu: bring bpu control signals into use (#1477)

sc: fix a bug on update threshold

bim, sc: hash between brs

sc: fix a bug on scUsed

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer

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tage_sc: use seperate wrbypass for each branch slot and use more entries for wrbypass in SC

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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tage-sc: merge two banks into one

bpu: fix fallThruAddr on fallThruError, implement ghist diff mechanism

sc: reduce an add operation at prediction path

sc: optimize timing for getCentered

ubtb: refactor prediction mechanism(temp commit)

Merge remote-tracking branch 'origin/change-fallThrough' into ubtb-refactor

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce lo

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

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core: refactor hardware performance counters (#1335)

This commit optimizes the coding style and timing for hardware
performance counters.

By default, performance counters are RegNext(RegNext(_)).

sc: reduce an add operation by not calculating absolute value of the sums

bpu: extract wrbypass to be a module

bpu: code clean ups, remove previous ghr impl

bpu: bring folded history into use, and use previous ghr to do difftest; move tage and ittage config to top

Merge branch 'master' into ftb-tail-shared