refactor(DFT): refactor `DFT` IO (#4530)

area(ICache): split ICache meta SRAM (#4468)

As per the requirements of the physical backend, split the ICache's Tag
SRAM into smaller blocks.

chore: fix several deprecation warning (#4352)

feat(dfx): integerate dfx components (#4312)

timing(icache): restore the relaxation of ICG for icache data (#4255)

Revert #4246

timing(icache): remove tag-related clock gating for timing (#4246)

timing(frontend): remove bad timing clock gating (#4223)

- Remove `mispred_mask` from ITTAGE update logic due to timing issues
- Remove `mispred_mask` from TAGE update logic due to timing issues
-

timing(frontend): remove bad timing clock gating (#4223)

- Remove `mispred_mask` from ITTAGE update logic due to timing issues
- Remove `mispred_mask` from TAGE update logic due to timing issues
- Disable clock gating in ICacheDataArray to improve timing

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feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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fix(ICache,ITLB): also flush itlb pipe when prefetchPipe s1_flush (#3996)

ITLB does not store `gpaddr` to save resources, instead it takes
`gpaddr` from L2TLB when gpf occurs, which poses a two-opt

fix(ICache,ITLB): also flush itlb pipe when prefetchPipe s1_flush (#3996)

ITLB does not store `gpaddr` to save resources, instead it takes
`gpaddr` from L2TLB when gpf occurs, which poses a two-option
requirement for the requestor (i.e. IPrefetchPipe):
1. resend the same `itlb.io.req.vaddr` until `itlb.io.resp.miss` is
pulled down
2. flush gpf entry in ITLB by pulling up `itlb.io.flushPipe`

Otherwise, ITLB is unable to handle the next gpf and the core hangs.

However, the first point cannot be guaranteed during the speculative
execution, as IPrefetchPipe sends request to ITLB at s0 stage and may
receive a flush request from BPU s3 stage, IFU or Backend at s1 stage,
then the same vaddr is never resend to ITLB.

Therefore, we must ensure that ITLB is flushed synchronously when
IPrefetchPipe s1 stage is flushed, thus satisfying the second point.
This PR implements this.

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refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fi

refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fix typo
- remove unused imports
- rename `ICacheMSHR.waymask` to `way` since it is not a mask
- use `idxBits` for `log2Up(nSets)`
- use `wayBits` for `log2Up(nWays)`
- use `foreach` instead of `map` when return value is not needed
- use `{}` instead of `()` for multi-line `foreach` and `map`

The generated verilog is checked and is identical with the original
(except `waymask` -> `way` & order changes).

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feat(ICache): re-fetch data from L2 if ECC error is detected (#3899)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)*
error recovery features.

Unlike DCache, data in ICache i

feat(ICache): re-fetch data from L2 if ECC error is detected (#3899)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)*
error recovery features.

Unlike DCache, data in ICache is always not dirty, so when it is
corrupted, we can always re-fetch from L2 cache.

Port & behavior changes:
- Add a `flush` port to metaArray, letting mainPipe be able to clear
valid_array before doing re-fetch, thereby preventing multi-hit in
ICache.
- if metaArray ECC error is detected, flush vSets in each way, since
`waymask` is unreliable.
- if dataArray ECC error is detected, flush the vSet in way specified by
`waymask`.
- metaArray / dataArray ECC errors will no longer raise access fault, as
they can be resolved by re-fetching. Raise af only when response from L2
is marked as corrupted.
- When ECC error is detected, mainPipe will send miss requests to L2
through MissUnit.

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feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\)

feat(frontend): add ClockGate at frontend SRAMTemplate (#3889)

* Add param `withClockGate` at SRAMTemplate
* when SRAM is single-port, use maskedClock for both array\.read\(\) and
array\.write\(\) to ensure single-port SRAM access.
* when SRAM is multi-port, the read and write ports of the multi-port
SRAM are gated using different clocks.

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docs: add acknowledgements (#3861)

area(DCache): reduce 8 way to 4 way (#3849)

fix(ICache): cancel prefetch when there is exception from backend (#3787)

fix(ICache): use PriorityMux instead of Mux1H for io.error (#3784)

mainPipe.io.errors is not ensured to be at-most-one-hot, ECC errors may
occur on both cachelines at the same time.

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

ICache: fix metaArray ECC check (#3419)

Currently, metaArray ECC check is valid 2 cycles after request:

https://github.com/OpenXiangShan/XiangShan/blob/49162c9ab67070931573c1d4a372e2c858a72716/sr

ICache: fix metaArray ECC check (#3419)

Currently, metaArray ECC check is valid 2 cycles after request:

https://github.com/OpenXiangShan/XiangShan/blob/49162c9ab67070931573c1d4a372e2c858a72716/src/main/scala/xiangshan/frontend/icache/ICache.scala#L262

However, prefetchPipe s1 handshakes with both WayLookup and prefetchPipe
s2 assuming that all signals of the metaArray.io.readResp are valid 1
cycle after the request, resulting in the error.

Simply removing this RegEnable may lead to problems with long timing
paths (metaArray (sram) -> ECC check (xor reduction) -> prefetchPipe s1
(wire) -> wayLookup (bypass, wire) -> mainPipe s0 (wire) -> mainPipe s1
(reg)), so no.

This PR may result in case-specific errors not being checked out, which
in turn results in additional fetch requests being sent to the L2 cache,
but does not causes corrupted data being sent to the backend. See
discussion in notes:

https://github.com/OpenXiangShan/XiangShan/blob/8b87b8dcbfd5945c5bd7815eb5e569fec252ddc6/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala#L279-L293

There are 2 more potential solutions described in an internal yuque
document, however, due to the complexity of implementation, area
overhead and other considerations, the current solution is considered to
be optimal.

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Frontend: implement prefetch.i support (RVA23 Zicbop) (#3396)

ICache: raise af if meta/data array ECC fail

In current design, meta/data array corruption does not raise any
exception (whether or not `io.csr_parity_enable === true.B`), which may
pose two probl

ICache: raise af if meta/data array ECC fail

In current design, meta/data array corruption does not raise any
exception (whether or not `io.csr_parity_enable === true.B`), which may
pose two problems:
1. When meta corrupt, `ptag` comparison result may be invalid, and thus
cache hit may be treated as a cache miss, thereby sending (pre)fetch
request to L2 cache incorrectly;
2. When meta/data/l2 corrupt, instruction data sent to the backend may
be invalid. Although the errors are sent to beu, which sends an
interrupt via plic, the timing of the interrupt is not as controllable
as an exception. It is therefore reasonable to mark invalid data as
access fault to keep it from execution.

This PR:
1. Raise af if meta/data array ECC fail (when `io.csr_parity_enable ===
true.B`), the priority of this af is lower than iTLB & PMP exceptions
2. Cancle (pre)fetching if meta array ECC fail (by merging
`meta_corrupt` exceptions to `s2_exception`)

Note:
RISC-V Machine ISA v1.13 (draft) introduced a "hardware error"
exception, described as:
> A Hardware Error exception is a synchronous exception triggered when
corrupted or uncorrectable data is accessed explicitly or implicitly by
an instruction. In this context, "data" encompasses all types of
information used within a RISC-V hart. Upon a hardware error exception,
the xepc register is set to the address of the instruction that
attempted to access corrupted data, while the xtval register is set
either to 0 or to the virtual address of an instruction fetch, load, or
store that attempted to access corrupted data. The priority of Hardware
Error exception is implementation-defined, but any given occurrence is
generally expected to be recognized at the point in the overall priority
order at which the hardware error is discovered.

Maybe it's better to raise hardware error instead of access fault when
ECC check failed. But it's draft and XiangShan backend does not
implement this exception code yet, so we still raise af here. This may
need to be modified in the future.

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build: purge chisel 3 and add deprecation check (#3250)

ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

L1CacheErrorInfo: code refactor for correct and convenient clockgate (#3044)

IFU,ICache: clock gating optimization (#2957)


Co-authored-by: Liang Sen <[email protected]>

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.

Signed-off-by: Yangyu Chen <[email protected]>

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