style(Bundles): move bundles to Bundles.scala (#4247)

fix(selectOldest): use `===` instead of `isNotBefore`

For instructions with vectors or other multiple `uop`, it is necessary to determine whether `robIdx` is the same before comparing `uopIdx`. Alth

fix(selectOldest): use `===` instead of `isNotBefore`

For instructions with vectors or other multiple `uop`, it is necessary to determine whether `robIdx` is the same before comparing `uopIdx`. Although there is no error if `isNotBefore` is used, we can use the clearer and more concise `===` to make the determination.

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feat(Zicclsm): refactoring misalign and support vector misalign

perf(uncache): mmio and nc share LQUncache; nc data can writeback to ldu1-2

feat(NCld): support WMO access for NC ld

* feat(LDU): add support for NC in LoadUnit

* feat(LQ,UB): add support for NC in load queue and uncache buffer

* chore(pbmt): add xsperf for nc ld statistic

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

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RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

--

RVA23: Support Zicclsm & Zama16b (Handling Unaligned Load Store by Hardware) (#3320)

This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches

---------

Co-authored-by: xiaofeibao <[email protected]>

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LSQ: optimize static clock gating coverage and fix x_value in vcs (#3176)

optimize LSQ static clock gating coverage, fix x_value in vcs

Revert "LSQ: optimize static clock gating coverage (#3023)" (#3055)

CoupledL2, Uncache, LSQ: support non-data error handling (#3042)

According to CHI specification, a non-data error should be reported when
an error is detected that is not related to data corruption

CoupledL2, Uncache, LSQ: support non-data error handling (#3042)

According to CHI specification, a non-data error should be reported when
an error is detected that is not related to data corruption. Typically
this error is reported for:
* An attempt to access a location that does not exist.
* An illegal access, such as a write to a read only location.
* An attempt to use a transaction type that is not supported.

While the second kind of errors can be resolved by PMA, the first and
the third kind of errors were not supported yet.

This commit implements non-data error handling path. MMIOBridge in
CoupledL2 transfers CHI `RespErr` field downwards into TileLink `denied`
field upwards. Uncache in DCache passes the error to LSQ to generate
access fault exception:
* For MMIO loads, UncacheBuffer writes back `exceptionVec` to LoadUnit
s0 and informs exception address to ExceptionBuffer at the same time.
* For MMIO stores, SQ writes back `exceptionVec` to Backend directly.

BTW, data error is still not supported.

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LSQ: optimize static clock gating coverage (#3023)

VLSU: fix faulty exception vaddr selection logic

Merge branch 'master' into vlsu-tmp-master

VLSU, lsq: support more than one vector pipeline

VLSU: support of vector store/load exception

rv64v: implement lsu & lsq vector datapath

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: compile emu successfully

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

fix errors in merge master into new-backend

DCacheWPU: update the latest version (#2095)

Co-authored-by: bugGenerator <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: Haoyuan Feng <fenghaoyuan19@mails

DCacheWPU: update the latest version (#2095)

Co-authored-by: bugGenerator <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: Haoyuan Feng <[email protected]>

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