xref: /XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala (revision 9e12e8edb26ee7dce62315a8f279ea9f61aa239d) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3._
21import chisel3.util._
22import utils._
23import utility._
24import xiangshan._
25import xiangshan.ExceptionNO._
26import xiangshan.frontend.FtqPtr
27import xiangshan.backend.fu.FuConfig._
28import xiangshan.backend.fu.fpu.FPU
29import xiangshan.backend.rob.RobLsqIO
30import xiangshan.backend.rob.RobPtr
31import xiangshan.mem.Bundles._
32import xiangshan.cache._
33import xiangshan.cache.wpu.ReplayCarry
34
35class LqExceptionBuffer(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper {
36  val enqPortNum = LoadPipelineWidth + VecLoadPipelineWidth + 1 // 1 for mmio bus non-data error
37
38  val io = IO(new Bundle() {
39    val redirect      = Flipped(Valid(new Redirect))
40    val req           = Vec(enqPortNum, Flipped(Valid(new LqWriteBundle)))
41    val exceptionAddr = new ExceptionAddrIO
42  })
43
44  val req_valid = RegInit(false.B)
45  val req = Reg(new LqWriteBundle)
46
47  // enqueue
48  // s1:
49  val s1_req = VecInit(io.req.map(_.bits))
50  val s1_valid = VecInit(io.req.map(x => x.valid))
51
52  // s2: delay 1 cycle
53  val s2_req = (0 until enqPortNum).map(i => {
54    RegEnable(s1_req(i), s1_valid(i))})
55  val s2_valid = (0 until enqPortNum).map(i =>
56    RegNext(s1_valid(i)) &&
57    !s2_req(i).uop.robIdx.needFlush(RegNext(io.redirect)) &&
58    !s2_req(i).uop.robIdx.needFlush(io.redirect)
59  )
60  val s2_has_exception = s2_req.map(x => ExceptionNO.selectByFu(x.uop.exceptionVec, LduCfg).asUInt.orR)
61
62  val s2_enqueue = Wire(Vec(enqPortNum, Bool()))
63  for (w <- 0 until enqPortNum) {
64    s2_enqueue(w) := s2_valid(w) && s2_has_exception(w)
65  }
66
67  when (req_valid && req.uop.robIdx.needFlush(io.redirect)) {
68    req_valid := s2_enqueue.asUInt.orR
69  } .elsewhen (s2_enqueue.asUInt.orR) {
70    req_valid := true.B
71  }
72
73  def selectOldest[T <: LqWriteBundle](valid: Seq[Bool], bits: Seq[T]): (Seq[Bool], Seq[T]) = {
74    assert(valid.length == bits.length)
75    if (valid.length == 0 || valid.length == 1) {
76      (valid, bits)
77    } else if (valid.length == 2) {
78      val res = Seq.fill(2)(Wire(ValidIO(chiselTypeOf(bits(0)))))
79      for (i <- res.indices) {
80        res(i).valid := valid(i)
81        res(i).bits := bits(i)
82      }
83      val oldest = Mux(valid(0) && valid(1),
84        Mux(isAfter(bits(0).uop.robIdx, bits(1).uop.robIdx) ||
85          (bits(0).uop.robIdx === bits(1).uop.robIdx && bits(0).uop.uopIdx > bits(1).uop.uopIdx), res(1), res(0)),
86        Mux(valid(0) && !valid(1), res(0), res(1)))
87      (Seq(oldest.valid), Seq(oldest.bits))
88    } else {
89      val left = selectOldest(valid.take(valid.length / 2), bits.take(bits.length / 2))
90      val right = selectOldest(valid.takeRight(valid.length - (valid.length / 2)), bits.takeRight(bits.length - (bits.length / 2)))
91      selectOldest(left._1 ++ right._1, left._2 ++ right._2)
92    }
93  }
94
95  val reqSel = selectOldest(s2_enqueue, s2_req)
96
97  when (req_valid) {
98    req := Mux(
99      reqSel._1(0) && (isAfter(req.uop.robIdx, reqSel._2(0).uop.robIdx) || (req.uop.robIdx === reqSel._2(0).uop.robIdx && req.uop.uopIdx > reqSel._2(0).uop.uopIdx)),
100      reqSel._2(0),
101      req)
102  } .elsewhen (s2_enqueue.asUInt.orR) {
103    req := reqSel._2(0)
104  }
105
106  io.exceptionAddr.vaddr  := req.fullva
107  io.exceptionAddr.vaNeedExt := req.vaNeedExt
108  io.exceptionAddr.isHyper := req.isHyper
109  io.exceptionAddr.vstart := req.uop.vpu.vstart
110  io.exceptionAddr.vl     := req.uop.vpu.vl
111  io.exceptionAddr.gpaddr := req.gpaddr
112  io.exceptionAddr.isForVSnonLeafPTE := req.isForVSnonLeafPTE
113
114  XSPerfAccumulate("exception", !RegNext(req_valid) && req_valid)
115
116  // end
117}
118