| #
46f74b57 |
| 06-May-2022 |
Haojin Tang <[email protected]> |
feat: parameterize load store (#1527)
* feat: parameterize load/store pipeline, etc.
* fix: use LoadPipelineWidth rather than LoadQueueSize
* fix: parameterize `rdataPtrExtNext`
* SBuffer:
feat: parameterize load store (#1527)
* feat: parameterize load/store pipeline, etc.
* fix: use LoadPipelineWidth rather than LoadQueueSize
* fix: parameterize `rdataPtrExtNext`
* SBuffer: fix idx update logic
* atomic: parameterize atomic logic in `MemBlock`
* StoreQueue: update allow enque requirement
* feat: support one load/store pipeline
* feat: parameterize `EnsbufferWidth`
* chore: resharp codes for better generated name
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|
| #
300ded30 |
| 04-Nov-2021 |
William Wang <[email protected]> |
Optimize dcache timing (#1195)
* dcache: do not check readline rmask
This should opt bank_conflict check timing
* dcache: block replace if store s1 valid
It takes quite long to generate way
Optimize dcache timing (#1195)
* dcache: do not check readline rmask
This should opt bank_conflict check timing
* dcache: block replace if store s1 valid
It takes quite long to generate way_en in mainpipe s1. As a result,
use s1 way_en to judge if replace should be blocked will cause severe
timing problem
Now we simply block replace if mainpipe.s1.valid
Refill timing to be optmized later
* sbuffer: delay sbuffer enqueue for 1 cycle
With store queue growing larger, read data from datamodule nearly
costs a whole cycle. Hence we delay sbuffer enqueue for 1 cycle
for better timing.
* dcache: reduce probe queue size
* dcache: replace probe pipe req RRArbiter with Arbiter
* dcache: reduce writeback queue size for timing opt
* dcache: delay wbqueue enqueue req for 1 cycle
Addr enqueue req will compare its addr with addrs in all writeback
entries to check if it should be blocked. Delay enqueue req will
give that process more time.
* dcache: set default replacer to setplru
It does not change current design
* dcache: fix wbqueue req_delayed deadlock
We delayed writeback queue enq for 1 cycle, missQ req does not
depend on wbQ enqueue. As a result, missQ req may be blocked
in req_delayed. When grant comes, that req should also be updated
* dcache: remove outdated require
* dcache: replace missReqArb RRArbiter with Arbiter
* perf: add detailed histogram for low dcache latency
* dcache: fix wbqueue entry alloc logic
* dcache: opt probe req timing
In current design, resv_set is maintained in dcache. All probe req
will be blocked if that addr is in resv_set.
However, checking if that addr is in resv_set costs almost half a cycle,
which causes severe timing problem.
Now when we update update_resv_set, all probe reqs will be blocked
in the next cycle. It should give Probe reservation set addr compare an
independent cycle, which will lead to better timing
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