xref: /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala (revision 45f43e6e5f88874a7573ff096d1e5c2855bd16c7) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3.experimental.requireIsChiselType
21import chisel3.reflect.DataMirror
22import chisel3._
23import chisel3.util._
24import xiangshan._
25import utils._
26import utility._
27import xiangshan.cache._
28import difftest._
29
30class DatamoduleResultBufferIO[T <: Data](gen: T)(implicit p: Parameters) extends XSBundle
31{
32  // val flush = Input(Bool())
33  val enq = Vec(EnsbufferWidth, Flipped(DecoupledIO(gen)))
34  val deq = Vec(EnsbufferWidth, DecoupledIO(gen))
35
36}
37
38class DatamoduleResultBuffer[T <: Data]
39(
40  gen: T,
41)(implicit p: Parameters) extends XSModule {
42
43  val genType = {
44    requireIsChiselType(gen)
45    gen
46  }
47
48  val io = IO(new DatamoduleResultBufferIO[T](gen))
49
50  val data = Reg(Vec(EnsbufferWidth, genType))
51  val valids = RegInit(VecInit(Seq.fill(EnsbufferWidth)(false.B)))
52  val enq_flag = RegInit(0.U(log2Up(EnsbufferWidth).W)) // head is entry 0
53  val deq_flag = RegInit(0.U(log2Up(EnsbufferWidth).W)) // tail is entry 0
54
55  val entry_allowin = Wire(Vec(EnsbufferWidth, Bool()))
56
57  (0 until EnsbufferWidth).foreach(index => {
58    io.deq(index).valid := valids(deq_flag + index.U) && (if (index == 0) 1.B else io.deq(index - 1).valid)
59    io.deq(index).bits := data(deq_flag + index.U)
60  })
61
62  (1 until EnsbufferWidth).foreach(i => {
63    assert(!(io.deq(i).valid && !io.deq(i - 1).valid))
64    assert(!(io.deq(i).ready && !io.deq(i - 1).ready))
65  })
66
67  (0 until EnsbufferWidth).foreach(
68    index => entry_allowin(index) := !valids(index) || (0 until EnsbufferWidth).map(i => io.deq(i).fire && deq_flag + i.U === index.U).reduce(_ || _)
69  )
70
71  (0 until EnsbufferWidth).foreach(
72    index => io.enq(index).ready := entry_allowin(enq_flag + index.U) && (if (index == 0) 1.B else io.enq(index - 1).ready)
73  )
74
75  (1 until EnsbufferWidth).foreach(i => {
76    assert(!(io.enq(i).ready && !io.enq(i - 1).ready))
77    assert(!(io.enq(i).valid && !io.enq(i - 1).valid))
78  })
79
80  (0 until EnsbufferWidth).foreach(index =>
81    when(io.deq(index).fire) {
82      valids(deq_flag + index.U) := 0.B
83      if (EnsbufferWidth > 1) deq_flag := deq_flag + index.U + 1.U
84    }
85  )
86
87  (0 until EnsbufferWidth).foreach(index =>
88    when(io.enq(index).fire) {
89      valids(enq_flag + index.U) := 1.B
90      data(enq_flag + index.U) := io.enq(index).bits
91      if (EnsbufferWidth > 1) enq_flag := enq_flag + index.U + 1.U
92    }
93  )
94}
95