| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 242 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
246 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
266 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
316 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
322 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
334 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
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| H A D | RegisterCoalescer.cpp | 1681 unsigned SubIdx) { in updateRegDefsUses()
2208 const unsigned SubIdx; member in __anon01e3b9040311::JoinVals
2373 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
2865 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, in usesLanes()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 236 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
240 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
260 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
310 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
316 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
328 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
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| H A D | ExpandPostRAPseudos.cpp | 91 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
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| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | DetectDeadLanes.cpp | 245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferUsedLanes() local
249 unsigned SubIdx = MI.getOperand(3).getImm(); in transferUsedLanes() local
269 unsigned SubIdx = MI.getOperand(2).getImm(); in transferUsedLanes() local
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); in transferDefinedLanes() local
325 unsigned SubIdx = MI.getOperand(3).getImm(); in transferDefinedLanes() local
337 unsigned SubIdx = MI.getOperand(2).getImm(); in transferDefinedLanes() local
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| H A D | RegisterCoalescer.cpp | 1244 unsigned SubIdx) { in updateRegDefsUses()
1708 const unsigned SubIdx; member in __anon5eeda8220211::JoinVals
1863 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, LaneBitmask LaneMask, in JoinVals()
2296 bool JoinVals::usesLanes(const MachineInstr &MI, unsigned Reg, unsigned SubIdx, in usesLanes()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 64 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
84 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| /aosp_15_r20/external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 444 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
493 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
534 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
626 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 449 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
553 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
652 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 208 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
781 unsigned SubIdx; in selectTruncOrPtrToInt() local
1194 unsigned SubIdx = X86::NoSubRegister; in emitExtractSubreg() local
1232 unsigned SubIdx = X86::NoSubRegister; in emitInsertSubreg() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 449 Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx, in ConstrainForSubReg()
498 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
554 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
653 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue(); in EmitRegSequence() local
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| /aosp_15_r20/external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg()
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass()
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| H A D | CodeGenRegisters.cpp | 469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
898 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses()
1565 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1927 for (const auto &SubIdx : SubRegIndices) { in inferSubClassWithSubReg() local
1959 for (auto &SubIdx : SubRegIndices) { in inferMatchingSuperRegClass() local
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| /aosp_15_r20/external/llvm/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
499 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 204 unsigned SubIdx = X86::NoSubRegister; in getSubRegIndex() local
742 unsigned SubIdx; in selectTruncOrPtrToInt() local
1201 unsigned SubIdx = X86::NoSubRegister; in emitExtractSubreg() local
1239 unsigned SubIdx = X86::NoSubRegister; in emitInsertSubreg() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 338 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
348 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
516 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 370 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
380 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
600 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 314 SDValue SubIdx = DAG.getNode(ISD::AND, dl, MVT::i32, {Idx, Mask}); in getIndexInWord32() local
681 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in extractHvxElementReg() local
742 SDValue SubIdx = getIndexInWord32(IdxV, ElemTy, DAG); in insertHvxElementReg() local
780 unsigned SubIdx; in extractHvxSubvectorReg() local
903 unsigned SubIdx = (Idx == 0) ? Hexagon::vsub_lo : Hexagon::vsub_hi; in insertHvxSubvectorReg() local
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 377 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
387 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
613 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 388 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
408 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
640 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 379 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
389 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
615 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 379 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName()
389 LaneBitmask getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask()
615 MCRegister getMatchingSuperReg(MCRegister Reg, unsigned SubIdx, in getMatchingSuperReg()
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineFunctionInfo.cpp | 187 unsigned SubIdx) { in getSpilledReg()
|