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/linux-6.14.4/include/uapi/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
39 #define MDIO_CTRL2 7 /* 10G control 2 */
40 #define MDIO_STAT2 8 /* 10G status 2 */
41 #define MDIO_PMA_TXDIS 9 /* 10G PMA/PMD transmit disable */
42 #define MDIO_PMA_RXDET 10 /* 10G PMA/PMD receive signal detect */
43 #define MDIO_PMA_EXTABLE 11 /* 10G PMA/PMD extended ability */
46 #define MDIO_AN_ADVERTISE 16 /* AN advertising (base page) */
47 #define MDIO_AN_LPA 19 /* AN LP abilities (base page) */
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/linux-6.14.4/arch/loongarch/kernel/
Dfpu.S1 /* SPDX-License-Identifier: GPL-2.0 */
7 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
12 #include <asm/asm-extable.h>
13 #include <asm/asm-offsets.h>
29 .macro sc_save_fp base argument
30 EX fst.d $f0, \base, (0 * FPU_REG_WIDTH)
31 EX fst.d $f1, \base, (1 * FPU_REG_WIDTH)
32 EX fst.d $f2, \base, (2 * FPU_REG_WIDTH)
33 EX fst.d $f3, \base, (3 * FPU_REG_WIDTH)
34 EX fst.d $f4, \base, (4 * FPU_REG_WIDTH)
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/linux-6.14.4/arch/loongarch/kvm/
Dswitch.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2023 Loongson Technology Corporation Limited
16 .macro kvm_save_host_gpr base argument
18 st.d $r\n, \base, HGPR_OFFSET(\n)
22 .macro kvm_restore_host_gpr base argument
24 ld.d $r\n, \base, HGPR_OFFSET(\n)
29 * Save and restore all GPRs except base register,
30 * and default value of base register is a2.
32 .macro kvm_save_guest_gprs base argument
33 .irp n,1,2,3,4,5,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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/linux-6.14.4/Documentation/networking/dsa/
Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
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/linux-6.14.4/arch/mips/kernel/
Dr4k_fpu.S8 * Multi-arch abstraction and asm macros for easier reading:
21 #include <asm/asm-offsets.h>
47 fpu_save_double a0 t0 t1 # clobbers t1
59 fpu_restore_double a0 t0 t1 # clobbers t1
92 * _save_fp_context() - save FP context from the FPU
93 * @a0 - pointer to fpregs field of sigcontext
94 * @a1 - pointer to fpc_csr field of sigcontext
102 cfc1 t1, fcr31
156 EX sw t1, 0(a1)
163 * _restore_fp_context() - restore FP context to the FPU
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Docteon_switch.S14 #include <asm/asm-offsets.h>
26 mfc0 t1, CP0_STATUS
27 LONG_S t1, THREAD_STATUS(a0)
40 sll t0, 7-LONGLOG-1
41 li t1, -32768 /* Base address of CVMSEG */
46 LONG_L t8, 0(t1) /* Load from CVMSEG */
48 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
49 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
53 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
76 PTR_ADDU t0, $28, _THREAD_SIZE - 32
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/linux-6.14.4/drivers/net/phy/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
64 Currently tested with mpc866ads and mpc8349e-mitx.
104 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
105 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
113 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
127 Currently supports the Asix Electronics PHY found in the X-Surf 100
136 found in the X-Surf 100 AX88796B package.
179 Currently supports the BCM8706 and BCM8727 10G Ethernet PHYs.
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Dphy-c45.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "mdio-open-alliance.h"
14 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
33 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
48 * genphy_c45_pma_resume - wakes up the PMA module
54 return -EOPNOTSUPP; in genphy_c45_pma_resume()
62 * genphy_c45_pma_suspend - suspends the PMA module
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/linux-6.14.4/include/linux/
Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2006-2009 Solarflare Communications Inc.
38 /* Bus address of the MDIO device (0-31) */
69 * up device-specific structures, if any
86 dev_set_drvdata(&mdio->dev, data); in mdiodev_set_drvdata()
91 return dev_get_drvdata(&mdio->dev); in mdiodev_get_drvdata()
105 get_device(&mdiodev->dev); in mdio_device_get()
129 * struct mdio_if_info - Ethernet controller MDIO interface
132 * non-zero unless @prtad = %MDIO_PRTAD_NONE.
154 #define MDIO_PRTAD_NONE (-1)
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/linux-6.14.4/arch/x86/crypto/
Dpoly1305-x86_64-cryptogams.pl2 # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
4 # Copyright (C) 2017-2018 Samuel Neves <[email protected]>. All Rights Reserved.
5 # Copyright (C) 2017-2019 Jason A. Donenfeld <[email protected]>. All Rights Reserved.
6 # Copyright (C) 2006-2017 CRYPTOGAMS by <[email protected]>. All Rights Reserved.
35 # Skylake-X system performance. Since we are likely to suppress
36 # AVX512F capability flag [at least on Skylake-X], conversion serves
43 # IALU/gcc-4.8(*) AVX(**) AVX2 AVX-512
44 # P4 4.46/+120% -
45 # Core 2 2.41/+90% -
46 # Westmere 1.88/+120% -
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/linux-6.14.4/lib/
Doverflow_kunit.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
4 * "Running tests with kunit_tool" at Documentation/dev-tools/kunit/start.rst
5 * ./tools/testing/kunit/kunit.py run overflow [--raw_output]
38 * Clang 13 and earlier generate unwanted libcalls for 64-bit tests on
39 * 32-bit hosts.
48 #define DEFINE_TEST_ARRAY_TYPED(t1, t2, t) \ argument
49 static const struct test_ ## t1 ## _ ## t2 ## __ ## t { \
50 t1 a; \
54 } t1 ## _ ## t2 ## __ ## t ## _tests[]
66 {U8_MAX, 1, 0, U8_MAX-1, U8_MAX, true, false, false},
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/linux-6.14.4/drivers/gpu/drm/i915/display/
Dintel_alpm.c1 // SPDX-License-Identifier: MIT
18 return intel_dp->alpm_dpcd & DP_ALPM_CAP; in intel_alpm_aux_wake_supported()
23 return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; in intel_alpm_aux_less_wake_supported()
30 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) in intel_alpm_init_dpcd()
33 intel_dp->alpm_dpcd = dpcd; in intel_alpm_init_dpcd()
39 * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2)
43 * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns
44 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )
46 * Link rates 5.4 - 8.1
47 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10
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/linux-6.14.4/drivers/ata/
Dpata_sis.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_sis.c - SiS ATA driver
9 * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
67 while (lap->device) { in sis_short_ata40()
68 if (lap->device == dev->device && in sis_short_ata40()
69 lap->subvendor == dev->subsystem_vendor && in sis_short_ata40()
70 lap->subdevice == dev->subsystem_device) in sis_short_ata40()
79 * sis_old_port_base - return PCI configuration base for dev
82 * Returns the base of the PCI configuration registers for this port
88 return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); in sis_old_port_base()
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/linux-6.14.4/arch/mips/cavium-octeon/
Docteon-memcpy.S18 #include <asm/asm-offsets.h>
30 * - src and dst don't overlap
31 * - src is readable
32 * - dst is writable
40 * - src is readable (no exceptions when reading src)
42 * - dst is writable (no exceptions when writing dst)
43 * __copy_user uses a non-standard calling convention; see
57 * 1- AT contain the address of the byte just past the end of the source
59 * 2- src_entry <= src < AT, and
60 * 3- (dst - src) == (dst_entry - src_entry),
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/linux-6.14.4/arch/arm/crypto/
Dpoly1305-armv4.pl2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause
5 # Written by Andy Polyakov, @dot-asm, initially for the OpenSSL
9 # IALU(*)/gcc-4.4 NEON
11 # ARM11xx(ARMv6) 7.78/+100% -
12 # Cortex-A5 6.35/+130% 3.00
13 # Cortex-A8 6.25/+115% 2.36
14 # Cortex-A9 5.10/+95% 2.55
15 # Cortex-A15 3.85/+85% 1.25(**)
18 # (*) this is for -march=armv6, i.e. with bunch of ldrb loading data;
19 # (**) these are trade-off results, they can be improved by ~8% but at
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/linux-6.14.4/tools/testing/selftests/hid/tests/
Dtest_sony.py2 # SPDX-License-Identifier: GPL-2.0
3 # -*- coding: utf-8 -*-
9 from .base import application_matches
43 for x in range(-32000, 32000, 4000):
51 # to inverse calibration, followed by calibration by hid-sony.
52 assert x - 1 <= value <= x + 1
54 for y in range(-32000, 32000, 4000):
61 assert y - 1 <= value <= y + 1
63 for z in range(-32000, 32000, 4000):
70 assert z - 1 <= value <= z + 1
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/linux-6.14.4/drivers/net/dsa/microchip/
Dlan937x_main.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019-2024 Microchip Technology Inc.
21 /* marker for ports without built-in PHY */
25 * lan9370_phy_addr - Mapping of LAN9370 switch ports to PHY addresses.
28 * where ports 1-4 are connected to integrated 100BASE-T1 PHYs, and
33 [0] = 2, /* Port 1, T1 AFE0 */
34 [1] = 3, /* Port 2, T1 AFE1 */
35 [2] = 5, /* Port 3, T1 AFE3 */
36 [3] = 6, /* Port 4, T1 AFE4 */
41 * lan9371_phy_addr - Mapping of LAN9371 switch ports to PHY addresses.
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/linux-6.14.4/drivers/pci/controller/dwc/
Dpcie-bt1.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Baikal-T1 PCIe controller driver
26 #include "pcie-designware.h"
28 /* Baikal-T1 System CCU control registers */
84 #define BT1_CCU_PCIE_PM_LINKSTATE_L2 BIT(10)
114 /* Baikal-T1 PCIe specific control registers */
130 /* Generic Baikal-T1 PCIe interface resources */
169 * Baikal-T1 MMIO space must be read/written by the dword-aligned
178 return -EINVAL; in bt1_pcie_read_mmio()
180 *val = readl(addr - ofs) >> ofs * BITS_PER_BYTE; in bt1_pcie_read_mmio()
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/linux-6.14.4/drivers/gpio/
Dgpio-viperboard.c1 // SPDX-License-Identifier: GPL-2.0+
46 u8 t1; member
77 …"gpio-a sampling freq in Hz (default is 1000Hz) valid values: 10, 100, 1000, 10000, 100000, 100000…
79 /* ----- begin of gipo a chip -------------------------------------------- */
86 struct vprbrd *vb = gpio->vb; in vprbrd_gpioa_get()
87 struct vprbrd_gpioa_msg *gamsg = (struct vprbrd_gpioa_msg *)vb->buf; in vprbrd_gpioa_get()
90 if (gpio->gpioa_out & (1 << offset)) in vprbrd_gpioa_get()
91 return !!(gpio->gpioa_val & (1 << offset)); in vprbrd_gpioa_get()
93 mutex_lock(&vb->lock); in vprbrd_gpioa_get()
95 gamsg->cmd = VPRBRD_GPIOA_CMD_GETIN; in vprbrd_gpioa_get()
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/linux-6.14.4/arch/arc/kernel/
Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
31 #include <asm/dsp-impl.h>
38 /* Part of U-boot ABI: see head.S */
49 unsigned int t0:1, t1:1; member
51 unsigned long base; member
67 { 0, "R3.10a"},
100 if (info->arcver < 0x34) in arcompact_mumbojumbo()
105 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s (%s ISA) %s%s%s\n", in arcompact_mumbojumbo()
108 IS_AVAIL1(be, "[Big-Endian]")); in arcompact_mumbojumbo()
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/linux-6.14.4/net/ethtool/
Dcommon.c1 // SPDX-License-Identifier: GPL-2.0-only
17 [NETIF_F_SG_BIT] = "tx-scatter-gather",
18 [NETIF_F_IP_CSUM_BIT] = "tx-checksum-ipv4",
19 [NETIF_F_HW_CSUM_BIT] = "tx-checksum-ip-generic",
20 [NETIF_F_IPV6_CSUM_BIT] = "tx-checksum-ipv6",
22 [NETIF_F_FRAGLIST_BIT] = "tx-scatter-gather-fraglist",
23 [NETIF_F_HW_VLAN_CTAG_TX_BIT] = "tx-vlan-hw-insert",
25 [NETIF_F_HW_VLAN_CTAG_RX_BIT] = "rx-vlan-hw-parse",
26 [NETIF_F_HW_VLAN_CTAG_FILTER_BIT] = "rx-vlan-filter",
27 [NETIF_F_HW_VLAN_STAG_TX_BIT] = "tx-vlan-stag-hw-insert",
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/linux-6.14.4/arch/mips/lib/
Dcsum_partial.S16 #include <asm/asm-offsets.h>
21 * As we are sharing code base with the mips32 tree (which use the o32 ABI
26 #undef t1
30 #define t1 $9 macro
31 #define t2 $10
164 lw t1, 0x04(src)
167 ADDC(sum, t1)
178 ld t1, 0x08(src)
180 ADDC(sum, t1)
182 CSUM_BIGCHUNK1(src, 0x00, sum, t0, t1, t3, t4)
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Dmemcpy.S23 * dma-coherent systems.
37 #include <asm/asm-offsets.h>
49 * - src and dst don't overlap
50 * - src is readable
51 * - dst is writable
59 * - src is readable (no exceptions when reading src)
61 * - dst is writable (no exceptions when writing dst)
62 * __copy_user uses a non-standard calling convention; see
63 * include/asm-mips/uaccess.h
76 * 1- AT contain the address of the byte just past the end of the source
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/linux-6.14.4/drivers/gpu/drm/i915/gt/
Dselftest_migrate.c1 // SPDX-License-Identifier: MIT
18 CHUNK_SZ - SZ_4K,
44 struct drm_i915_private *i915 = migrate->context->engine->i915; in copy()
56 sz = src->base.size; in copy()
94 if (err != -EDEADLK && err != -EINTR && err != -ERESTARTSYS) in copy()
110 err = -ETIME; in copy()
122 err = -EINVAL; in copy()
151 GEM_BUG_ON(ce->vm != ce->engine->gt->migrate.context->vm); in intel_context_copy_ccs()
154 GEM_BUG_ON(ce->ring->size < SZ_64K); in intel_context_copy_ccs()
157 if (HAS_64K_PAGES(ce->engine->i915)) in intel_context_copy_ccs()
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/linux-6.14.4/arch/s390/lib/
Dcrc32le-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
18 #include "crc32-vx.h"
20 /* Vector register range containing CRC-32 constants */
22 #define CONST_R2R1 10
29 * The CRC-32 constant block contains reduction constants to fold and
32 * For the CRC-32 variants, the constants are precomputed according to
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