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/linux-6.14.4/drivers/fpga/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # FPGA framework configuration
6 menuconfig FPGA config
7 tristate "FPGA Configuration Framework"
10 kernel. The FPGA framework adds an FPGA manager class and FPGA
13 if FPGA
15 config FPGA_MGR_SOCFPGA
16 tristate "Altera SOCFPGA FPGA Manager"
19 FPGA manager driver support for Altera SOCFPGA.
21 config FPGA_MGR_SOCFPGA_A10
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Daltera-ps-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Manage Altera FPGA firmware that is loaded over SPI using the passive
18 #include <linux/fpga/fpga-mgr.h>
39 struct gpio_desc *config; member
75 { .compatible = "altr,fpga-passive-serial", .data = &c5_data },
76 { .compatible = "altr,fpga-arria10-passive-serial", .data = &a10_data },
83 struct altera_ps_conf *conf = mgr->priv; in altera_ps_state()
85 if (gpiod_get_value_cansleep(conf->status)) in altera_ps_state()
103 struct altera_ps_conf *conf = mgr->priv; in altera_ps_write_init()
107 conf->info_flags = info->flags; in altera_ps_write_init()
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Dof-fpga-region.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Region - Device Tree support for FPGA programming under Linux
5 * Copyright (C) 2013-2016 Altera Corporation
8 #include <linux/fpga/fpga-bridge.h>
9 #include <linux/fpga/fpga-mgr.h>
10 #include <linux/fpga/fpga-region.h>
22 { .compatible = "fpga-region", },
28 * of_fpga_region_find - find FPGA region
29 * @np: device node of FPGA Region
31 * Caller will need to put_device(&region->dev) when done.
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Dxilinx-core.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Common parts of the Xilinx Spartan6 and 7 Series FPGA manager drivers.
10 #include "xilinx-core.h"
13 #include <linux/fpga/fpga-mgr.h>
19 struct xilinx_fpga_core *core = mgr->priv; in get_done_gpio()
22 ret = gpiod_get_value(core->done); in get_done_gpio()
24 dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret); in get_done_gpio()
38 * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
41 * @mgr: The FPGA manager object
45 * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
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Dsocfpga.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera SOCFPGA
5 * Copyright (C) 2013-2015 Altera Corporation
9 #include <linux/fpga/fpga-mgr.h>
96 /* In power-up order. Reverse for power-down. */
98 "FPGA-1.5V",
99 "FPGA-1.1V",
100 "FPGA-2.5V",
136 return readl(priv->fpga_base_addr + reg_offset); in socfpga_fpga_readl()
142 writel(value, priv->fpga_base_addr + reg_offset); in socfpga_fpga_writel()
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Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
3 * FPGA Manager Driver for Altera Arria10 SoCFPGA
5 * Copyright (C) 2015-2016 Altera Corporation
10 #include <linux/fpga/fpga-mgr.h>
54 /* FPGA CD Ratio Value */
65 * struct a10_fpga_priv - private data for fpga manager
67 * @fpga_data_addr: iomap for single address data register to FPGA
116 * Partial Reconfiguration : 16bit Passive Parallel
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
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Daltera-cvp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
9 * Manage Altera FPGA firmware using PCIe CvP.
15 #include <linux/fpga/fpga-mgr.h>
62 #define DRV_NAME "altera-cvp"
63 #define ALTERA_CVP_MGR_NAME "Altera CvP FPGA Manager"
69 /* Optional CvP config error status check for debugging */
98 return pci_read_config_byte(conf->pci_dev, conf->vsec_offset + where, in altera_read_config_byte()
105 return pci_read_config_dword(conf->pci_dev, conf->vsec_offset + where, in altera_read_config_dword()
112 return pci_write_config_dword(conf->pci_dev, conf->vsec_offset + where, in altera_write_config_dword()
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/linux-6.14.4/Documentation/devicetree/bindings/fpga/
Dfpga-region.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <[email protected]>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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/linux-6.14.4/Documentation/fpga/
Ddfl.rst2 FPGA Device Feature List (DFL) Framework Overview
7 - Enno Luebbers <[email protected]>
8 - Xiao Guangrong <[email protected]>
9 - Wu Hao <[email protected]>
10 - Xu Yilun <[email protected]>
12 The Device Feature List (DFL) FPGA framework (and drivers according to
15 configure, enumerate, open and access FPGA accelerators on platforms which
17 enables system level management functions such as FPGA reconfiguration.
24 walk through these predefined data structures to enumerate FPGA features:
25 FPGA Interface Unit (FIU), Accelerated Function Unit (AFU) and Private Features,
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/linux-6.14.4/include/linux/firmware/intel/
Dstratix10-svc-client.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
12 * fpga: for FPGA configuration
15 #define SVC_CLIENT_FPGA "fpga"
34 * FPGA configuration, FPGA should be in user mode.
59 * Set to FPGA configuration type (full or partial).
65 * timeout value used in Stratix10 FPGA manager driver.
77 * enum stratix10_svc_command_code - supported service commands
79 * @COMMAND_NOOP: do 'dummy' request for integration/debug/trouble-shooting
81 * @COMMAND_RECONFIG: ask for FPGA configuration preparation, return status
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/linux-6.14.4/include/linux/firmware/
Dxlnx-zynqmp.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2014-2021 Xilinx
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
108 * Firmware FPGA Manager flags
109 * XILINX_ZYNQMP_PM_FPGA_FULL: FPGA full reconfiguration
110 * XILINX_ZYNQMP_PM_FPGA_PARTIAL: FPGA partial reconfiguration
115 /* FPGA Status Reg */
145 * XPM_EVENT_ERROR_MASK_DDRMC_NCR: Error event mask for DDRMC MC Non-Correctable ECC Error.
203 /* PMU-FW return status codes */
524 * enum pm_sd_config_type - PM SD configuration.
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/linux-6.14.4/drivers/firmware/xilinx/
Dzynqmp.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2022 Xilinx, Inc.
6 * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
14 #include <linux/arm-smccc.h>
27 #include <linux/firmware/xlnx-zynqmp.h>
28 #include <linux/firmware/xlnx-event-manager.h>
29 #include "zynqmp-debug.h"
36 /* BOOT_PIN_CTRL- Used to control the mode pins after boot */
38 /* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */
53 * struct zynqmp_devinfo - Structure for Zynqmp device instance
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/linux-6.14.4/drivers/gpu/drm/amd/display/dc/
Ddc_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
58 /* Emulation on FPGA, in "Maximus" System.
60 * (access to non-DC registers will hang FPGA) */
62 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces
145 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/
147 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/
237 Must be zero for wired displays and non-zero for
330 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */
402 unsigned int src_height; /* input active height (half-active height in interlaced mode) */
408 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */
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/linux-6.14.4/drivers/char/xilinx_hwicap/
Dxilinx_hwicap.c26 * (c) Copyright 2007-2008 Xilinx Inc.
36 * This is the code behind /dev/icap* -- it allows a user-space
64 * user-space application code that uses this device. The simplest
69 * Note that unless foo.bit is an appropriately constructed partial
71 * currently programmed in the FPGA.
218 * hwicap_command_desync - Send a DESYNC command to the ICAP port.
235 buffer[index++] = hwicap_type_1_write(drvdata->config_regs->CMD) | 1; in hwicap_command_desync()
244 return drvdata->config->set_configuration(drvdata, in hwicap_command_desync()
249 * hwicap_get_configuration_register - Query a configuration register.
281 status = drvdata->config->set_configuration(drvdata, in hwicap_get_configuration_register()
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/linux-6.14.4/drivers/firmware/
Dstratix10-svc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018, Intel Corporation
19 #include <linux/firmware/intel/stratix10-smc.h>
20 #include <linux/firmware/intel/stratix10-svc-client.h>
24 * SVC_NUM_DATA_IN_FIFO - number of struct stratix10_svc_data in the FIFO
26 * SVC_NUM_CHANNEL - number of channel supported by service layer driver
28 * FPGA_CONFIG_DATA_CLAIM_TIMEOUT_MS - claim back the submitted buffer(s)
29 * from the secure world for FPGA manager to reuse, or to free the buffer(s)
30 * when all bit-stream data had be send.
32 * FPGA_CONFIG_STATUS_TIMEOUT_SEC - poll the FPGA configuration status,
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/linux-6.14.4/drivers/net/ethernet/sfc/
Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
29 * we shouldn't touch PCIe config. */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
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/linux-6.14.4/drivers/infiniband/hw/hfi1/
Dchip.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
101 #define emulator_rev(dd) ((dd)->irev >> 8)
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