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Searched refs:max_render_backends (Results 1 – 20 of 20) sorted by relevance

/aosp_15_r20/external/mesa3d/src/amd/common/
H A Dac_surface_test_common.h27 info->max_render_backends = 16; in init_vega10()
42 info->max_render_backends = 16; in init_vega20()
58 info->max_render_backends = 2; in init_raven()
73 info->max_render_backends = 1; in init_raven2()
223 info.max_render_backends = info.gfx_level == GFX10 || testcase->banks_or_pkrs ? 2 : 1; in get_radeon_info()
H A Dac_cmdbuf.c183 const unsigned num_rb = MIN2(info->max_render_backends, 16); in ac_set_raster_config()
383 if (info->max_render_backends <= 4) { in gfx10_init_graphics_preamble_state()
548 uint64_t rb_mask = BITFIELD64_MASK(info->max_render_backends); in gfx10_init_graphics_preamble_state()
747 uint64_t rb_mask = BITFIELD64_MASK(info->max_render_backends); in gfx12_init_graphics_preamble_state()
H A Dac_gpu_info.c1091 info->max_render_backends = device_info.num_rb_pipes; in ac_query_gpu_info()
1094 info->max_render_backends = 2; in ac_query_gpu_info()
1416 unsigned num_rb_per_se = info->max_render_backends / info->max_se; in ac_query_gpu_info()
1464 if (info->max_render_backends == 1) { in ac_query_gpu_info()
1554 info->max_render_backends; in ac_query_gpu_info()
2056 fprintf(f, " max_render_backends = %i\n", info->max_render_backends); in ac_print_gpu_info()
2241 unsigned num_rb = MIN2(info->max_render_backends, 16); in ac_get_harvested_configs()
H A Dac_gpu_info.h292 uint32_t max_render_backends; /* number of render backends incl. disabled ones */ member
H A Dac_shadowed_regs.c3625 uint64_t rb_mask = BITFIELD64_MASK(info->max_render_backends); in ac_create_shadowing_ib_preamble()
H A Dac_surface.c357 if (info->max_render_backends == 1) { in ac_get_supported_modifiers()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_binning.c29 util_logbase2_ceil(sscreen->info.max_render_backends / sscreen->info.max_se); in si_find_bin_size()
294 const unsigned num_rbs = sctx->screen->info.max_render_backends; in gfx10_get_bin_sizes()
471 if (sscreen->info.max_render_backends > 4 && ps_can_kill && db_can_reject_z_trivially && in si_emit_dpbb_state()
H A Dsi_query.c448 result->u32 = sctx->screen->info.max_render_backends; in si_query_sw_get_result()
591 unsigned max_rbs = screen->info.max_render_backends; in si_query_hw_prepare_buffer()
660 query->result_size = 16 * sscreen->info.max_render_backends; in si_query_hw_create()
937 fence_va = va + sctx->screen->info.max_render_backends * 16; in si_query_hw_do_emit_stop()
1282 unsigned max_rbs = sctx->screen->info.max_render_backends; in si_get_hw_query_result_shader_params()
1365 unsigned max_rbs = sscreen->info.max_render_backends; in si_query_hw_add_result()
H A Dsi_fence.c86 16 * sscreen->info.max_render_backends, 256); in si_cp_release_mem()
91 assert(16 * ctx->screen->info.max_render_backends <= scratch->b.b.width0); in si_cp_release_mem()
H A Dsi_pipe.c536 PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256); in si_create_context()
1358 sscreen->use_ngg_culling = sscreen->info.max_render_backends >= 2 && in radeonsi_screen_create_impl()
1366 sscreen->info.max_render_backends >= 2 && in radeonsi_screen_create_impl()
1397 if ((sscreen->info.has_dedicated_vram && sscreen->info.max_render_backends > 4) || in radeonsi_screen_create_impl()
H A Dsi_state.c4980 unsigned num_rb = MIN2(sscreen->info.max_render_backends, 16); in si_set_raster_config()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_query.c415 result->u32 = rctx->screen->info.max_render_backends; in r600_query_sw_get_result()
522 unsigned max_rbs = rscreen->info.max_render_backends; in r600_query_hw_prepare_buffer()
607 query->result_size = 16 * rscreen->info.max_render_backends; in r600_query_hw_create()
806 fence_va = va + ctx->screen->info.max_render_backends * 16 - 8; in r600_query_hw_do_emit_stop()
1067 unsigned max_rbs = rctx->screen->info.max_render_backends; in r600_get_hw_query_params()
1158 unsigned max_rbs = rscreen->info.max_render_backends; in r600_query_hw_add_result()
1830 ctx->screen->info.max_render_backends = 8; in r600_query_fix_enabled_rb_mask()
1832 max_rbs = ctx->screen->info.max_render_backends; in r600_query_fix_enabled_rb_mask()
2102 if (((struct r600_common_screen*)rctx->b.screen)->info.max_render_backends > 0) in r600_query_init()
H A Dr600_pipe_common.c1352 printf("num_render_backends = %i\n", rscreen->info.max_render_backends); in r600_common_screen_init()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/winsys/null/
H A Dradv_null_winsys.c130 gpu_info->max_render_backends = pci_ids[gpu_info->family].num_render_backends; in radv_null_winsys_query_info()
/aosp_15_r20/external/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_winsys.c383 &ws->info.max_render_backends)) in do_winsys_init()
423 ws->info.enabled_rb_mask = u_bit_consecutive(0, ws->info.max_render_backends); in do_winsys_init()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/
H A Dradv_query.c131 unsigned db_count = pdev->info.max_render_backends; in build_occlusion_query_shader()
1134 pool->stride = 16 * pdev->info.max_render_backends; in radv_create_query_pool()
1304 uint32_t db_count = pdev->info.max_render_backends; in radv_GetQueryPoolResults()
H A Dradv_physical_device.c465 …if ((pdev->info.has_dedicated_vram && pdev->info.max_render_backends > 4) || pdev->info.gfx_level … in radv_get_binning_settings()
2115 pdev->use_ngg_culling = pdev->use_ngg && pdev->info.max_render_backends > 1 && in radv_physical_device_try_create()
H A Dradv_cmd_buffer.c1279 const unsigned rb_count = pdev->info.max_render_backends; in radv_gfx10_compute_bin_size()
1567 …unsigned log_num_rb_per_se = util_logbase2_ceil(pdev->info.max_render_backends / pdev->info.max_se… in radv_gfx9_compute_bin_size()
7216 unsigned num_db = pdev->info.max_render_backends; in radv_BeginCommandBuffer()
/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D21.0.0.rst2065 - ac: rename num_render_backends -\> max_render_backends
H A D22.0.0.rst3684 - radv: fix max_render_backends for Sienna Cichlid null winsys