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Searched refs:nir_io_add_const_offset_to_base (Results 1 – 13 of 13) sorted by relevance

/aosp_15_r20/external/mesa3d/src/intel/compiler/elk/
H A Delk_nir.c257 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in elk_nir_lower_vs_inputs()
381 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in elk_nir_lower_vue_inputs()
429 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in elk_nir_lower_tes_inputs()
541 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in elk_nir_lower_fs_inputs()
569 nir_io_add_const_offset_to_base(nir, nir_var_shader_out); in elk_nir_lower_tcs_outputs()
/aosp_15_r20/external/mesa3d/src/intel/compiler/
H A Dbrw_nir.c362 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in brw_nir_lower_vs_inputs()
476 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in brw_nir_lower_vue_inputs()
524 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in brw_nir_lower_tes_inputs()
630 nir_io_add_const_offset_to_base(nir, nir_var_shader_in); in brw_nir_lower_fs_inputs()
658 nir_io_add_const_offset_to_base(nir, nir_var_shader_out); in brw_nir_lower_tcs_outputs()
/aosp_15_r20/external/mesa3d/src/amd/vulkan/nir/
H A Dradv_nir_lower_io.c72 NIR_PASS(_, nir, nir_io_add_const_offset_to_base, nir_var_shader_in | nir_var_shader_out); in radv_nir_lower_io()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_shader_nir.c176 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in | nir_var_shader_out); in si_nir_late_opts()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/panfrost/
H A Dpan_shader.c129 NIR_PASS_V(s, nir_io_add_const_offset_to_base, in panfrost_shader_compile()
/aosp_15_r20/external/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_nir.cpp774 NIR_PASS_V(sh, nir_io_add_const_offset_to_base, io_modes); in r600_lower_and_optimize_nir()
/aosp_15_r20/external/mesa3d/src/compiler/nir/
H A Dnir_lower_io.c3037 nir_io_add_const_offset_to_base(nir_shader *nir, nir_variable_mode modes) in nir_io_add_const_offset_to_base() function
3279 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in | nir_var_shader_out); in nir_lower_io_passes()
H A Dnir.h5617 bool nir_io_add_const_offset_to_base(nir_shader *nir, nir_variable_mode modes);
/aosp_15_r20/external/mesa3d/src/asahi/vulkan/
H A Dhk_shader.c1041 NIR_PASS(_, nir, nir_io_add_const_offset_to_base, in hk_compile_shader()
/aosp_15_r20/external/mesa3d/src/asahi/lib/
H A Dagx_nir_lower_gs.c1246 NIR_PASS(_, gs, nir_io_add_const_offset_to_base, in agx_nir_lower_gs()
/aosp_15_r20/external/mesa3d/docs/relnotes/
H A D20.3.0.rst1145 - nir: Handle per-view io in nir_io_add_const_offset_to_base()
3325 - nir: update IO semantics in nir_io_add_const_offset_to_base
3343 - nir: fix a bug in is_dual_slot in nir_io_add_const_offset_to_base
4334 - nir/lower_io: change nir_io_add_const_offset_to_base to use bitfield modes
4335 - radeonsi: call nir_io_add_const_offset_to_base only once per shader
4337 - radv: call nir_io_add_const_offset_to_base for FS outputs
H A D22.2.0.rst3820 - radeonsi: run nir_io_add_const_offset_to_base for TES/TCS as late optimizations
5191 - nir: call nir_metadata_preserve in nir_io_add_const_offset_to_base
/aosp_15_r20/external/mesa3d/src/gallium/drivers/zink/
H A Dzink_compiler.c4184 NIR_PASS_V(nir, nir_io_add_const_offset_to_base, nir_var_shader_in | in zink_shader_compile()