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Searched defs:access (Results 1 – 5 of 5) sorted by relevance

/XiangShan/src/main/scala/xiangshan/cache/mmu/
H A DTLBStorage.scala107 val access = io.access(i) constant
H A DMMUBundle.scala433 val access = Vec(ports, new ReplaceAccessBundle(nSets, nWays)) constant
497 val access = Vec(Width, Flipped(new ReplaceAccessBundle(nSets, nWays))) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/
H A DMissQueue.scala457 val access = RegInit(false.B) constant
H A DMainPipe.scala72 val access = Bool() constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DDCacheWrapper.scala362 val access = Bool() // cache line has been accessed by load / store constant