1// See LICENSE.SiFive for license details. 2 3package device 4 5import chisel3._ 6import chisel3.util._ 7 8import bus.axi4._ 9import utils._ 10 11class AXI4Timer extends AXI4SlaveModule(new AXI4Lite) { 12 val clk = 50000 // 50MHz / 1000 13 val tick = Counter(true.B, clk)._2 14 val ms = Counter(tick, 0x40000000)._1 15 in.r.bits.data := ms 16} 17