1package xiangshan.backend.issue 2 3import org.chipsalliance.cde.config.Parameters 4import chisel3.util._ 5import utils.SeqUtils 6import xiangshan.backend.BackendParams 7import xiangshan.backend.Bundles._ 8import xiangshan.backend.datapath.WakeUpSource 9import xiangshan.backend.datapath.WbConfig.PregWB 10 11case class SchdBlockParams( 12 issueBlockParams: Seq[IssueBlockParams], 13 numPregs : Int, 14 numDeqOutside : Int, 15 schdType : SchedulerType, 16 rfDataWidth : Int, 17) { 18 var backendParam: BackendParams = null 19 20 def isMemSchd: Boolean = schdType == MemScheduler() 21 22 def isIntSchd: Boolean = schdType == IntScheduler() 23 24 def isFpSchd: Boolean = schdType == FpScheduler() 25 26 def isVfSchd: Boolean = schdType == VfScheduler() 27 28 def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum 29 30 def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum 31 32 def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum 33 34 def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum 35 36 def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum 37 38 def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum 39 40 def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum 41 42 def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum 43 44 def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum 45 46 def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum 47 48 def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum 49 50 def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum 51 52 def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum 53 54 def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum 55 56 def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum 57 58 def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum 59 60 def HyuCnt: Int = issueBlockParams.map(_.HyuCnt).sum 61 62 def LdExuCnt: Int = issueBlockParams.map(_.LdExuCnt).sum 63 64 def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum 65 66 def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum 67 68 def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum 69 70 def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum 71 72 def numExu: Int = issueBlockParams.map(_.exuBlockParams.count(!_.fakeUnit)).sum 73 74 def hasCSR = CsrCnt > 0 75 76 def hasFence = FenceCnt > 0 77 78 def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum 79 80 def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum 81 82 def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum 83 84 def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum 85 86 def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum 87 88 def needOg2Resp: Boolean = isVfSchd || isMemSchd && issueBlockParams.map(_.needOg2Resp).reduce(_ || _) 89 90 def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _) 91 92 def needSrcVxrm: Boolean = issueBlockParams.map(_.needSrcVxrm).reduce(_ || _) 93 94 def writeVConfig: Boolean = issueBlockParams.map(_.writeVConfig).reduce(_ || _) 95 96 def writeVType: Boolean = issueBlockParams.map(_.writeVType).reduce(_ || _) 97 98 def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum 99 100 def pregIdxWidth: Int = log2Up(numPregs) 101 102 def numWakeupFromWB: Int = schdType match { 103 case IntScheduler() | VfScheduler() => 8 104 case MemScheduler() => 16 // Todo 105 case _ => 0 106 } 107 108 def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum 109 110 def numFpRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numFpSrc).sum).sum 111 112 def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numVecSrc).sum).sum 113 114 def numV0RfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numV0Src).sum).sum 115 116 def numVlRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numVlSrc).sum).sum 117 118 def bindBackendParam(param: BackendParams): Unit = { 119 backendParam = param 120 } 121 122 def numWriteRegCache: Int = issueBlockParams.map(_.numWriteRegCache).sum 123 124 def needWriteRegCache: Boolean = numWriteRegCache > 0 125 126 def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = { 127 MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle)) 128 } 129 130 def genExuInputCopySrcBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = { 131 MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledCopySrcBundle)) 132 } 133 134 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = { 135 MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle)) 136 } 137 138 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = { 139 MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle)) 140 } 141 142 def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = { 143 MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle)) 144 } 145 146 def wakeUpInExuSources: Seq[WakeUpSource] = { 147 issueBlockParams 148 .flatMap(_.wakeUpInExuSources) 149 .distinctBy(_.name) 150 } 151 152 def wakeUpOutExuSources: Seq[WakeUpSource] = { 153 issueBlockParams 154 .flatMap(_.wakeUpOutExuSources) 155 .distinctBy(_.name) 156 } 157 158 def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 159 MixedVec(this.wakeUpInExuSources.map(x => { 160 val param = x.getExuParam(backendParam.allExuParams) 161 val isCopyPdest = param.copyWakeupOut 162 val copyNum = param.copyNum 163 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 164 }) 165 ) 166 } 167 168 def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = { 169 MixedVec(this.wakeUpOutExuSources.map(x => { 170 val param = x.getExuParam(backendParam.allExuParams) 171 val isCopyPdest = param.copyWakeupOut 172 val copyNum = param.copyNum 173 ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam, isCopyPdest, copyNum)) 174 }) 175 ) 176 } 177 178 def genWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 179 val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 180 case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 181 case _ => Seq() 182 } 183 val fpBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match { 184 case FpScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 185 case _ => Seq() 186 } 187 val vfBundle = schdType match { 188 case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 189 case _ => Seq() 190 } 191 val v0Bundle = schdType match { 192 case VfScheduler() | MemScheduler() => backendParam.getV0WBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 193 case _ => Seq() 194 } 195 val vlBundle = schdType match { 196 case VfScheduler() | MemScheduler() => backendParam.getVlWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq 197 case _ => Seq() 198 } 199 MixedVec(intBundle ++ fpBundle ++ vfBundle ++ v0Bundle ++ vlBundle) 200 } 201 202 def genIntWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 203 MixedVec(backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 204 } 205 206 def genFpWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 207 MixedVec(backendParam.getFpWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 208 } 209 210 def genVfWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 211 MixedVec(backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 212 } 213 214 def genV0WBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 215 MixedVec(backendParam.getV0WBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 216 } 217 218 def genVlWBWakeUpSinkValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = { 219 MixedVec(backendParam.getVlWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq) 220 } 221 222 // cfgs(issueIdx)(exuIdx)(set of exu's wb) 223 def getWbCfgs: Seq[Seq[Set[PregWB]]] = { 224 this.issueBlockParams.map(_.getWbCfgs) 225 } 226} 227