xref: /XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala (revision 39c59369af6e7d78fa72e13aae3735f1a6e98f5c) 
1package xiangshan.backend.issue
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3.util._
5import utils.SeqUtils
6import xiangshan.backend.BackendParams
7import xiangshan.backend.Bundles._
8import xiangshan.backend.datapath.WakeUpSource
9import xiangshan.backend.datapath.WbConfig.PregWB
10
11case class SchdBlockParams(
12  issueBlockParams: Seq[IssueBlockParams],
13  numPregs        : Int,
14  numDeqOutside   : Int,
15  schdType        : SchedulerType,
16  rfDataWidth     : Int,
17  numUopIn        : Int,
18) {
19  var backendParam: BackendParams = null
20
21  def isMemSchd: Boolean = schdType == MemScheduler()
22
23  def isIntSchd: Boolean = schdType == IntScheduler()
24
25  def isVfSchd: Boolean = schdType == VfScheduler()
26
27  def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum
28
29  def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum
30
31  def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum
32
33  def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum
34
35  def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum
36
37  def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum
38
39  def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum
40
41  def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum
42
43  def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum
44
45  def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum
46
47  def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum
48
49  def FmiscCnt: Int = issueBlockParams.map(_.FmiscCnt).sum
50
51  def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum
52
53  def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum
54
55  def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum
56
57  def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum
58
59  def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum
60
61  def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum
62
63  def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum
64
65  def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum
66
67  def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum
68
69  def numExu: Int = issueBlockParams.map(_.exuBlockParams.size).sum
70
71  def hasCSR = CsrCnt > 0
72
73  def hasFence = FenceCnt > 0
74
75  def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum
76
77  def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum
78
79  def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum
80
81  def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum
82
83  def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum
84
85  def numPcReadPort = {
86    val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0)
87    if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0
88  }
89
90  def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _)
91
92  def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum
93
94  def pregIdxWidth: Int = log2Up(numPregs)
95
96  def numWakeupFromWB: Int = schdType match {
97    case IntScheduler() | VfScheduler() => 8
98    case MemScheduler() => 16 // Todo
99    case _ => 0
100  }
101
102  def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum
103
104  def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum
105
106  def bindBackendParam(param: BackendParams): Unit = {
107    backendParam = param
108  }
109
110  def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = {
111    MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle))
112  }
113
114  def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = {
115    MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle))
116  }
117
118  def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = {
119    MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle))
120  }
121
122  def genExuBypassValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuBypassBundle]]] = {
123    MixedVec(this.issueBlockParams.map(_.genExuBypassValidBundle))
124  }
125
126  def wakeUpInExuSources: Seq[WakeUpSource] = {
127    SeqUtils.distinctBy(
128      issueBlockParams
129        .flatMap(_.wakeUpInExuSources)
130    )(_.name)
131  }
132
133  def wakeUpOutExuSources: Seq[WakeUpSource] = {
134    SeqUtils.distinctBy(
135      issueBlockParams
136        .flatMap(_.wakeUpOutExuSources)
137    )(_.name)
138  }
139
140  def genIQWakeUpInValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = {
141    MixedVec(this.wakeUpInExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam))))
142  }
143
144  def genIQWakeUpOutValidBundle(implicit p: Parameters): MixedVec[ValidIO[IssueQueueIQWakeUpBundle]] = {
145    MixedVec(this.wakeUpOutExuSources.map(x => ValidIO(new IssueQueueIQWakeUpBundle(backendParam.getExuIdx(x.name), backendParam))))
146  }
147
148  def genWBWakeUpSinkValidBundle: MixedVec[ValidIO[IssueQueueWBWakeUpBundle]] = {
149    val intBundle: Seq[ValidIO[IssueQueueWBWakeUpBundle]] = schdType match {
150      case IntScheduler() | MemScheduler() => backendParam.getIntWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq
151      case _ => Seq()
152    }
153    val vfBundle = schdType match {
154      case VfScheduler() | MemScheduler() => backendParam.getVfWBExeGroup.map(x => ValidIO(new IssueQueueWBWakeUpBundle(x._2.map(_.exuIdx), backendParam))).toSeq
155      case _ => Seq()
156    }
157    MixedVec(intBundle ++ vfBundle)
158  }
159
160  // cfgs(issueIdx)(exuIdx)(set of exu's wb)
161  def getWbCfgs: Seq[Seq[Set[PregWB]]] = {
162    this.issueBlockParams.map(_.getWbCfgs)
163  }
164}
165