1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility.HasCircularQueuePtrHelper 23import utility.ParallelPriorityMux 24import utility.GatedValidRegNext 25import utility.XSError 26import xiangshan._ 27 28abstract class RegType 29case object Reg_I extends RegType 30case object Reg_F extends RegType 31case object Reg_V extends RegType 32case object Reg_V0 extends RegType 33case object Reg_Vl extends RegType 34 35class RatReadPort(ratAddrWidth: Int)(implicit p: Parameters) extends XSBundle { 36 val hold = Input(Bool()) 37 val addr = Input(UInt(ratAddrWidth.W)) 38 val data = Output(UInt(PhyRegIdxWidth.W)) 39} 40 41class RatWritePort(ratAddrWidth: Int)(implicit p: Parameters) extends XSBundle { 42 val wen = Bool() 43 val addr = UInt(ratAddrWidth.W) 44 val data = UInt(PhyRegIdxWidth.W) 45} 46 47class RenameTable(reg_t: RegType)(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper { 48 49 // params alias 50 private val numVecRegSrc = backendParams.numVecRegSrc 51 private val numVecRatPorts = numVecRegSrc 52 53 val readPortsNum = reg_t match { 54 case Reg_I => 2 55 case Reg_F => 3 56 case Reg_V => 3 57 case Reg_V0 => 1 58 case Reg_Vl => 1 59 } 60 val rdataNums = reg_t match { 61 case Reg_I => 32 62 case Reg_F => 32 63 case Reg_V => 31 // no v0 64 case Reg_V0 => 1 // v0 65 case Reg_Vl => 1 // vl 66 } 67 val renameTableWidth = reg_t match { 68 case Reg_I => log2Ceil(IntLogicRegs) 69 case Reg_F => log2Ceil(FpLogicRegs) 70 case Reg_V => log2Ceil(VecLogicRegs) 71 case Reg_V0 => log2Ceil(V0LogicRegs) 72 case Reg_Vl => log2Ceil(VlLogicRegs) 73 } 74 75 val io = IO(new Bundle { 76 val redirect = Input(Bool()) 77 val readPorts = Vec(readPortsNum * RenameWidth, new RatReadPort(renameTableWidth)) 78 val specWritePorts = Vec(RabCommitWidth, Input(new RatWritePort(renameTableWidth))) 79 val archWritePorts = Vec(RabCommitWidth, Input(new RatWritePort(renameTableWidth))) 80 val old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 81 val need_free = Vec(RabCommitWidth, Output(Bool())) 82 val snpt = Input(new SnapshotPort) 83 val diffWritePorts = if (backendParams.basicDebugEn) Some(Vec(RabCommitWidth * MaxUopSize, Input(new RatWritePort(renameTableWidth)))) else None 84 val debug_rdata = if (backendParams.debugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 85 val diff_rdata = if (backendParams.basicDebugEn) Some(Vec(rdataNums, Output(UInt(PhyRegIdxWidth.W)))) else None 86 val debug_v0 = if (backendParams.debugEn) reg_t match { 87 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 88 case _ => None 89 } else None 90 val diff_v0 = if (backendParams.debugEn) reg_t match { 91 case Reg_V0 => Some(Output(UInt(PhyRegIdxWidth.W))) 92 case _ => None 93 } else None 94 val debug_vl = if (backendParams.debugEn) reg_t match { 95 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 96 case _ => None 97 } else None 98 val diff_vl = if (backendParams.debugEn) reg_t match { 99 case Reg_Vl => Some(Output(UInt(PhyRegIdxWidth.W))) 100 case _ => None 101 } else None 102 }) 103 104 // speculative rename table 105 val rename_table_init = reg_t match { 106 case Reg_I => VecInit.fill (IntLogicRegs)(0.U(PhyRegIdxWidth.W)) 107 case Reg_F => VecInit.tabulate(FpLogicRegs)(_.U(PhyRegIdxWidth.W)) 108 case Reg_V => VecInit.tabulate(VecLogicRegs)(_.U(PhyRegIdxWidth.W)) 109 case Reg_V0 => VecInit.tabulate(V0LogicRegs)(_.U(PhyRegIdxWidth.W)) 110 case Reg_Vl => VecInit.tabulate(VlLogicRegs)(_.U(PhyRegIdxWidth.W)) 111 } 112 val spec_table = RegInit(rename_table_init) 113 val spec_table_next = WireInit(spec_table) 114 // arch state rename table 115 val arch_table = RegInit(rename_table_init) 116 val arch_table_next = WireDefault(arch_table) 117 // old_pdest 118 val old_pdest = RegInit(VecInit.fill(RabCommitWidth)(0.U(PhyRegIdxWidth.W))) 119 val need_free = RegInit(VecInit.fill(RabCommitWidth)(false.B)) 120 121 // For better timing, we optimize reading and writing to RenameTable as follows: 122 // (1) Writing at T0 will be actually processed at T1. 123 // (2) Reading is synchronous now. 124 // (3) RAddr at T0 will be used to access the table and get data at T0. 125 // (4) WData at T0 is bypassed to RData at T1. 126 val t1_redirect = GatedValidRegNext(io.redirect, false.B) 127 val t1_raddr = io.readPorts.map(p => RegEnable(p.addr, !p.hold)) 128 val t1_rdata_use_t1_raddr = VecInit(t1_raddr.map(spec_table(_))) 129 val t1_wSpec = RegNext(Mux(io.redirect, 0.U.asTypeOf(io.specWritePorts), io.specWritePorts)) 130 131 val t1_snpt = RegNext(io.snpt, 0.U.asTypeOf(io.snpt)) 132 val t2_snpt = RegNext(t1_snpt, 0.U.asTypeOf(io.snpt)) 133 134 val snapshots = SnapshotGenerator(spec_table, t1_snpt.snptEnq, t1_snpt.snptDeq, t1_redirect, t1_snpt.flushVec) 135 136 // WRITE: when instruction commits or walking 137 val t1_wSpec_addr = t1_wSpec.map(w => Mux(w.wen, UIntToOH(w.addr), 0.U)) 138 for ((next, i) <- spec_table_next.zipWithIndex) { 139 val matchVec = t1_wSpec_addr.map(w => w(i)) 140 val wMatch = ParallelPriorityMux(matchVec.reverse, t1_wSpec.map(_.data).reverse) 141 // When there's a flush, we use arch_table to update spec_table. 142 next := Mux( 143 RegNext(t1_redirect), 144 Mux(t2_snpt.useSnpt, snapshots(t2_snpt.snptSelect)(i), arch_table(i)), 145 Mux(VecInit(matchVec).asUInt.orR, wMatch, spec_table(i)) 146 ) 147 } 148 spec_table := spec_table_next 149 150 // READ: decode-rename stage 151 for ((r, i) <- io.readPorts.zipWithIndex) { 152 val t0_bypass = io.specWritePorts.map(w => w.wen && Mux(r.hold, w.addr === t1_raddr(i), w.addr === r.addr)) 153 val t1_bypass = RegNext(Mux(io.redirect, 0.U.asTypeOf(VecInit(t0_bypass)), VecInit(t0_bypass))) 154 val bypass_data = ParallelPriorityMux(t1_bypass.reverse, t1_wSpec.map(_.data).reverse) 155 r.data := Mux(t1_bypass.asUInt.orR, bypass_data, t1_rdata_use_t1_raddr(i)) 156 } 157 158 for ((w, i) <- io.archWritePorts.zipWithIndex) { 159 when (w.wen) { 160 arch_table_next(w.addr) := w.data 161 } 162 val arch_mask = VecInit.fill(PhyRegIdxWidth)(w.wen).asUInt 163 old_pdest(i) := 164 MuxCase(arch_table(w.addr) & arch_mask, 165 io.archWritePorts.take(i).reverse.map(x => (x.wen && x.addr === w.addr, x.data & arch_mask))) 166 } 167 arch_table := arch_table_next 168 169 for (((old, free), i) <- (old_pdest zip need_free).zipWithIndex) { 170 val hasDuplicate = old_pdest.take(i).map(_ === old) 171 val blockedByDup = if (i == 0) false.B else VecInit(hasDuplicate).asUInt.orR 172 free := VecInit(arch_table.map(_ =/= old)).asUInt.andR && !blockedByDup 173 } 174 175 io.old_pdest := old_pdest 176 io.need_free := need_free 177 io.debug_rdata.foreach{ x => reg_t match { 178 case Reg_V => x := arch_table.drop(1).take(rdataNums) 179 case _ => x := arch_table.take(rdataNums) 180 } 181 } 182 io.debug_v0.foreach(_ := arch_table(0)) 183 io.debug_vl.foreach(_ := arch_table(0)) 184 if (env.EnableDifftest || env.AlwaysBasicDiff) { 185 val difftest_table = RegInit(rename_table_init) 186 val difftest_table_next = WireDefault(difftest_table) 187 188 for (w <- io.diffWritePorts.get) { 189 when(w.wen) { 190 difftest_table_next(w.addr) := w.data 191 } 192 } 193 difftest_table := difftest_table_next 194 195 io.diff_rdata.foreach{ x => reg_t match { 196 case Reg_V => x := difftest_table.drop(1).take(rdataNums) 197 case _ => x := difftest_table.take(rdataNums) 198 } 199 } 200 io.diff_v0.foreach(_ := difftest_table(0)) 201 io.diff_vl.foreach(_ := difftest_table(0)) 202 } 203 else { 204 io.diff_rdata.foreach(_ := 0.U.asTypeOf(io.debug_rdata.get)) 205 io.diff_v0.foreach(_ := 0.U) 206 io.diff_vl.foreach(_ := 0.U) 207 } 208} 209 210class RenameTableWrapper(implicit p: Parameters) extends XSModule { 211 212 // params alias 213 private val numVecRegSrc = backendParams.numVecRegSrc 214 private val numVecRatPorts = numVecRegSrc 215 216 val io = IO(new Bundle() { 217 val redirect = Input(Bool()) 218 val rabCommits = Input(new RabCommitIO) 219 val diffCommits = if (backendParams.basicDebugEn) Some(Input(new DiffCommitIO)) else None 220 val intReadPorts = Vec(RenameWidth, Vec(2, new RatReadPort(IntLogicRegs))) 221 val intRenamePorts = Vec(RenameWidth, Input(new RatWritePort(IntLogicRegs))) 222 val fpReadPorts = Vec(RenameWidth, Vec(3, new RatReadPort(FpLogicRegs))) 223 val fpRenamePorts = Vec(RenameWidth, Input(new RatWritePort(FpLogicRegs))) 224 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, new RatReadPort(VecLogicRegs))) 225 val vecRenamePorts = Vec(RenameWidth, Input(new RatWritePort(VecLogicRegs))) 226 val v0ReadPorts = Vec(RenameWidth, new RatReadPort(V0LogicRegs)) 227 val v0RenamePorts = Vec(RenameWidth, Input(new RatWritePort(V0LogicRegs))) 228 val vlReadPorts = Vec(RenameWidth, new RatReadPort(VlLogicRegs)) 229 val vlRenamePorts = Vec(RenameWidth, Input(new RatWritePort(VlLogicRegs))) 230 231 val int_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 232 val fp_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 233 val vec_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 234 val v0_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 235 val vl_old_pdest = Vec(RabCommitWidth, Output(UInt(PhyRegIdxWidth.W))) 236 val int_need_free = Vec(RabCommitWidth, Output(Bool())) 237 val snpt = Input(new SnapshotPort) 238 239 // for debug assertions 240 val debug_int_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 241 val debug_fp_rat = if (backendParams.debugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 242 val debug_vec_rat = if (backendParams.debugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 243 val debug_v0_rat = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 244 val debug_vl_rat = if (backendParams.debugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 245 246 // for difftest 247 val diff_int_rat = if (backendParams.basicDebugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 248 val diff_fp_rat = if (backendParams.basicDebugEn) Some(Vec(32, Output(UInt(PhyRegIdxWidth.W)))) else None 249 val diff_vec_rat = if (backendParams.basicDebugEn) Some(Vec(31, Output(UInt(PhyRegIdxWidth.W)))) else None 250 val diff_v0_rat = if (backendParams.basicDebugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 251 val diff_vl_rat = if (backendParams.basicDebugEn) Some(Vec(1,Output(UInt(PhyRegIdxWidth.W)))) else None 252 }) 253 254 val intRat = Module(new RenameTable(Reg_I)) 255 val fpRat = Module(new RenameTable(Reg_F)) 256 val vecRat = Module(new RenameTable(Reg_V)) 257 val v0Rat = Module(new RenameTable(Reg_V0)) 258 val vlRat = Module(new RenameTable(Reg_Vl)) 259 260 io.debug_int_rat .foreach(_ := intRat.io.debug_rdata.get) 261 io.diff_int_rat .foreach(_ := intRat.io.diff_rdata.get) 262 intRat.io.readPorts <> io.intReadPorts.flatten 263 intRat.io.redirect := io.redirect 264 intRat.io.snpt := io.snpt 265 io.int_old_pdest := intRat.io.old_pdest 266 io.int_need_free := intRat.io.need_free 267 val intDestValid = io.rabCommits.info.map(_.rfWen) 268 for ((arch, i) <- intRat.io.archWritePorts.zipWithIndex) { 269 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && intDestValid(i) 270 arch.addr := io.rabCommits.info(i).ldest 271 arch.data := io.rabCommits.info(i).pdest 272 XSError(arch.wen && arch.addr === 0.U && arch.data =/= 0.U, "pdest for $0 should be 0\n") 273 } 274 for ((spec, i) <- intRat.io.specWritePorts.zipWithIndex) { 275 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && intDestValid(i) 276 spec.addr := io.rabCommits.info(i).ldest 277 spec.data := io.rabCommits.info(i).pdest 278 XSError(spec.wen && spec.addr === 0.U && spec.data =/= 0.U, "pdest for $0 should be 0\n") 279 } 280 for ((spec, rename) <- intRat.io.specWritePorts.zip(io.intRenamePorts)) { 281 when (rename.wen) { 282 spec.wen := true.B 283 spec.addr := rename.addr 284 spec.data := rename.data 285 } 286 } 287 if (backendParams.basicDebugEn) { 288 for ((diff, i) <- intRat.io.diffWritePorts.get.zipWithIndex) { 289 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).rfWen 290 diff.addr := io.diffCommits.get.info(i).ldest 291 diff.data := io.diffCommits.get.info(i).pdest 292 } 293 } 294 295 // debug read ports for difftest 296 io.debug_fp_rat.foreach(_ := fpRat.io.debug_rdata.get) 297 io.diff_fp_rat .foreach(_ := fpRat.io.diff_rdata.get) 298 fpRat.io.readPorts <> io.fpReadPorts.flatten 299 fpRat.io.redirect := io.redirect 300 fpRat.io.snpt := io.snpt 301 io.fp_old_pdest := fpRat.io.old_pdest 302 303 for ((arch, i) <- fpRat.io.archWritePorts.zipWithIndex) { 304 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).fpWen 305 arch.addr := io.rabCommits.info(i).ldest 306 arch.data := io.rabCommits.info(i).pdest 307 } 308 for ((spec, i) <- fpRat.io.specWritePorts.zipWithIndex) { 309 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).fpWen 310 spec.addr := io.rabCommits.info(i).ldest 311 spec.data := io.rabCommits.info(i).pdest 312 } 313 for ((spec, rename) <- fpRat.io.specWritePorts.zip(io.fpRenamePorts)) { 314 when (rename.wen) { 315 spec.wen := true.B 316 spec.addr := rename.addr 317 spec.data := rename.data 318 } 319 } 320 if (backendParams.basicDebugEn) { 321 for ((diff, i) <- fpRat.io.diffWritePorts.get.zipWithIndex) { 322 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).fpWen 323 diff.addr := io.diffCommits.get.info(i).ldest 324 diff.data := io.diffCommits.get.info(i).pdest 325 } 326 } 327 328 // debug read ports for difftest 329 io.debug_vec_rat .foreach(_ := vecRat.io.debug_rdata.get) 330 io.diff_vec_rat .foreach(_ := vecRat.io.diff_rdata.get) 331 vecRat.io.readPorts <> io.vecReadPorts.flatten 332 vecRat.io.redirect := io.redirect 333 vecRat.io.snpt := io.snpt 334 io.vec_old_pdest := vecRat.io.old_pdest 335 336 //TODO: RM the donTouch 337 if(backendParams.debugEn) { 338 dontTouch(vecRat.io) 339 } 340 for ((arch, i) <- vecRat.io.archWritePorts.zipWithIndex) { 341 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vecWen 342 arch.addr := io.rabCommits.info(i).ldest 343 arch.data := io.rabCommits.info(i).pdest 344 } 345 for ((spec, i) <- vecRat.io.specWritePorts.zipWithIndex) { 346 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vecWen 347 spec.addr := io.rabCommits.info(i).ldest 348 spec.data := io.rabCommits.info(i).pdest 349 } 350 for ((spec, rename) <- vecRat.io.specWritePorts.zip(io.vecRenamePorts)) { 351 when (rename.wen) { 352 spec.wen := true.B 353 spec.addr := rename.addr 354 spec.data := rename.data 355 } 356 } 357 if (backendParams.basicDebugEn) { 358 for ((diff, i) <- vecRat.io.diffWritePorts.get.zipWithIndex) { 359 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vecWen 360 diff.addr := io.diffCommits.get.info(i).ldest 361 diff.data := io.diffCommits.get.info(i).pdest 362 } 363 } 364 365 // debug read ports for difftest 366 io.debug_v0_rat.foreach(_ := v0Rat.io.debug_rdata.get) 367 io.diff_v0_rat.foreach(_ := v0Rat.io.diff_rdata.get) 368 v0Rat.io.readPorts <> io.v0ReadPorts 369 v0Rat.io.redirect := io.redirect 370 v0Rat.io.snpt := io.snpt 371 io.v0_old_pdest := v0Rat.io.old_pdest 372 373 if (backendParams.debugEn) { 374 dontTouch(v0Rat.io) 375 } 376 for ((arch, i) <- v0Rat.io.archWritePorts.zipWithIndex) { 377 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).v0Wen 378 arch.addr := io.rabCommits.info(i).ldest 379 arch.data := io.rabCommits.info(i).pdest 380 } 381 for ((spec, i) <- v0Rat.io.specWritePorts.zipWithIndex) { 382 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).v0Wen 383 spec.addr := io.rabCommits.info(i).ldest 384 spec.data := io.rabCommits.info(i).pdest 385 } 386 for ((spec, rename) <- v0Rat.io.specWritePorts.zip(io.v0RenamePorts)) { 387 when(rename.wen) { 388 spec.wen := true.B 389 spec.addr := rename.addr 390 spec.data := rename.data 391 } 392 } 393 if (backendParams.basicDebugEn) { 394 for ((diff, i) <- v0Rat.io.diffWritePorts.get.zipWithIndex) { 395 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).v0Wen 396 diff.addr := io.diffCommits.get.info(i).ldest 397 diff.data := io.diffCommits.get.info(i).pdest 398 } 399 } 400 401 // debug read ports for difftest 402 io.debug_vl_rat.foreach(_ := vlRat.io.debug_rdata.get) 403 io.diff_vl_rat.foreach(_ := vlRat.io.diff_rdata.get) 404 vlRat.io.readPorts <> io.vlReadPorts 405 vlRat.io.redirect := io.redirect 406 vlRat.io.snpt := io.snpt 407 io.vl_old_pdest := vlRat.io.old_pdest 408 409 if (backendParams.debugEn) { 410 dontTouch(vlRat.io) 411 } 412 for ((arch, i) <- vlRat.io.archWritePorts.zipWithIndex) { 413 arch.wen := io.rabCommits.isCommit && io.rabCommits.commitValid(i) && io.rabCommits.info(i).vlWen 414 arch.addr := io.rabCommits.info(i).ldest 415 arch.data := io.rabCommits.info(i).pdest 416 } 417 for ((spec, i) <- vlRat.io.specWritePorts.zipWithIndex) { 418 spec.wen := io.rabCommits.isWalk && io.rabCommits.walkValid(i) && io.rabCommits.info(i).vlWen 419 spec.addr := io.rabCommits.info(i).ldest 420 spec.data := io.rabCommits.info(i).pdest 421 } 422 for ((spec, rename) <- vlRat.io.specWritePorts.zip(io.vlRenamePorts)) { 423 when(rename.wen) { 424 spec.wen := true.B 425 spec.addr := rename.addr 426 spec.data := rename.data 427 } 428 } 429 if (backendParams.basicDebugEn) { 430 for ((diff, i) <- vlRat.io.diffWritePorts.get.zipWithIndex) { 431 diff.wen := io.diffCommits.get.isCommit && io.diffCommits.get.commitValid(i) && io.diffCommits.get.info(i).vlWen 432 diff.addr := io.diffCommits.get.info(i).ldest 433 diff.data := io.diffCommits.get.info(i).pdest 434 } 435 } 436} 437